adsp-21991 Analog Devices, Inc., adsp-21991 Datasheet - Page 26

• Manufacturer Part Number: adsp-21991
• Description: Mixed Signal Dsp Controller
• Manufacturer: Analog Devices, Inc.

ADSP-21991
External Port Write Cycle Timing
Table 8
The external port lets systems extend read/write accesses in three
ways: wait states, ACK input, and combined wait states and
ACK. To add waits with ACK, the DSP must see ACK low at
Table 8. External Port Write Cycle Timing
1
2
3
4
5
6
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
These are timing parameters that are based on worst-case operating conditions.
W = (number of wait states specified in wait register)
Write hold cycle–memory select control registers (MS
Write wait state count (E_WWC) = 0
Write wait state count (E_WWC) = 1
AKW
DWSAK
CSWS
AWS
WSCS
WSA
WW
CDA
CDD
DSW
DHW
DHW
WWR
EMICLK
and
is the External Memory Interface clock period. t
Figure 9
1, 2
MS3–0
A21–0
D15–0
IOMS
BMS
ACK
ACK Strobe Pulsewidth
ACK Delay from XMS Low
Chip Select Asserted to WR Asserted Delay
Address Valid to WR Setup and Delay
WR Deasserted to Chip Select Deasserted
WR Deasserted to Address Invalid
Data Valid to WR Deasserted Setup
WR Deasserted to Data Invalid Hold Time; E_WHC
WR Deasserted to Data Invalid Hold Time; E_WHC
WR Deasserted to WR, RD Asserted
WR Strobe Pulsewidth
WR to Data Enable Access Delay
WR to Data Disable Access Delay
WR
RD
describe external port write operations.
t
CSWS
t
t
DWSAK
CDA
t
AWS
Figure 9. External Port Write Cycle Timing
t
HCLK
EMICLK
CTL).
t
AKW
is the peripheral clock period.
.
t
–26–
WW
the rising edge of EMI clock. ACK low causes the DSP to wait,
and the DSP requires two EMI clock cycles after ACK goes high
to finish the access. For more information, see the External Port
chapter in the ADSP-2199x DSP Hardware Reference.
t
DSW
4, 5
4, 6
Min
12.5
0.5t
0.5t
0.5t
0.5t
t
0.5t
t
3.4
t
t
EMICLK
EMICLK
EMICLK
HCLK
EMICLK
EMICLK
EMICLK
EMICLK
EMICLK
–2+W
+1+W
+3.4
–4
–3
–4
–3
–3
t
t
CDD
DHW
t
t
WSCS
WSA
t
WWR
3
3
Max
0.5t
0
0.5t
t
EMICLK
EMICLK
EMICLK
+7+W
–1
+4
3
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns