adsp-21991 Analog Devices, Inc., adsp-21991 Datasheet - Page 32

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adsp-21991

Manufacturer Part Number
adsp-21991
Description
Mixed Signal Dsp Controller
Manufacturer
Analog Devices, Inc.
Datasheet

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ADSP-21991
Serial Peripheral Interface Port—Master Timing
Table 12
Table 12. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPID
HSPID
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPID
HDSPID
and
CPHA = 0
CPHA = 1
(CPOL = 1)
(CPOL = 0)
Figure 15
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
Data Input Valid to SCLK Edge (Data Input Setup)
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCLK Edge to SPISEL High
Sequential Transfer Delay
SCLK Edge to Data Output Valid (Data Out Delay)
SCLK Edge to Data Output Invalid (Data Out Hold)
(INPUT)
SPISEL
SPISEL Low to First SCLK Edge
(INPUT)
SCLK
SCLK
MISO
MISO
MOSI
MOSI
describe SPI port master operations.
t
SSPID
t
SDSCIM
t
Figure 15. Serial Peripheral Interface (SPI) Port—Master Timing
SPICLM
t
VALID
SSPID
MSB
t
SPICHM
MSB
VALID
MSB
t
HSPID
t
SPICLM
t
MSB
DDSPID
t
HSPID
t
DDSPID
t
SPICHM
–32–
t
HDSPID
VALID
t
t
LSB
SPICLK
SSPID
t
HDSPID
VALID
LSB
LSB
Min
8
1
2t
2t
2t
4t
2t
2t
0
0
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
t
HDSM
LSB
–3
–3
–3
–1
–3
–2
t
HSPID
t
SPITDM
Max
6
5
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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