adsp-21991 Analog Devices, Inc., adsp-21991 Datasheet - Page 27

• Manufacturer Part Number: adsp-21991
• Description: Mixed Signal Dsp Controller
• Manufacturer: Analog Devices, Inc.

External Port Read Cycle Timing
Table 9
For additional information on the ACK signal, see the discussion
on Page
Table 9. External Port Read Cycle Timing
1
2
3
REV. 0
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
These are timing parameters that are based on worst-case operating conditions.
W = (number of wait states specified in wait register)
AKW
RDA
ADA
SDA
SD
HRD
DRSAK
CSRS
ARS
RSCS
RW
RSA
RWR
EMICLK
and
is the External Memory Interface clock period. t
26.
Figure 10
1, 2
MS3--0
A21–0
D15–0
ACK Strobe Pulsewidth
Address Valid to Data Access Setup
Chip Select Asserted to Data Access Setup
Data Valid to RD Deasserted Setup
ACK Delay from XMS Low
Chip Select Asserted to RD Asserted Delay
Address Valid to RD Setup and Delay
IOMS
RD Deasserted to Data Invalid Hold
RD Deasserted to Chip Select Deasserted Setup
RD Strobe Pulsewidth
RD Deasserted to Address Invalid Setup
RD Deasserted to WR, RD Asserted
RD Asserted to Data Access Setup
BMS
ACK
WR
RD
describe external port read operations.
t
CSRS
t
Figure 10. External Port Read Cycle Timing
DRSAK
t
ARS
t
HCLK
EMICLK
is the peripheral clock period.
t
.
CDA
t
t
t
RDA
ADA
SDA
–27–
t
AKW
t
RW
t
S D
Min
t
5
0
0.5t
0.5t
0.5t
t
0.5t
t
HCLK
EMICLK
HCLK
EMICLK
EMICLK
EMICLK
HCLK
–2+W
–2
–3
–3
–2
t
t
H R D
RWR
t
3
t
RSA
RSCS
Max
t
t
t
0.5t
EMICLK
EMICLK
EMICLK
ADSP-21991
EMICLK
–5+W
+W
+W
–1
3
3
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns