dac1208d750 NXP Semiconductors, dac1208d750 Datasheet - Page 96

dac1208d750

Manufacturer Part Number

dac1208d750

Description

Dac1208d750 Dual 12-bit Dac; Up To 750 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface

Manufacturer

NXP Semiconductors

Datasheet

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NXP Semiconductors

Table 114. KOUT_FLAG register (address 05h) bit

Table 115. K28_LN0_FLAG register (address 06h) bit

Table 116. K28_LN1_FLAG register (address 07h) bit

Table 117. K28_LN2_FLAG register (address 08h) bit

Table 118. K28_LN3_FLAG register (address 09h) bit

Table 119. KOUT_UNEXPECTED_FLAG register

Table 120. LOCK_CNT_MON_LN01 register

Table 121. LOCK_CNT_MON_LN23 register

Table 122. CS_STATE_LNX register (address 0Dh) bit

Table 123. RST_BUF_ERR_FLAGS register

Table 124. INTR_MISC_ENA register (address 0Fh)

Table 125. FLAG_CNT_LSB_LN0 register

Table 126. FLAG_CNT_MSB_LN0 register

Table 127. FLAG_CNT_LSB_LN1 register

Table 128. FLAG_CNT_MSB_LN1 register

Table 129. FLAG_CNT_LSB_LN2 register

Table 130. FLAG_CNT_MSB_LN2 register

Table 131. FLAG_CNT_LSB_LN3 register

Table 132. FLAG_CNT_MSB_LN3 register

Table 133. BER_LEVEL_LSB register (address 18h)

Table 134. BER_LEVEL_MSB register (address 19h)

Table 135. INTR_ENA register (address 1Ah) bit

Table 136. CNTRL_FLAGCNT_LN01 register

Table 137. CNTRL_FLAGCNT_LN23 register

Table 138. MON_FLAGS_RESET register

DAC1208D750

Product data sheet

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

(address 0Ah) bit description . . . . . . . . . . . . . .72

(address 0Bh) bit description . . . . . . . . . . . . . .72

(address 0Ch) bit description . . . . . . . . . . . . . .72

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

(address 0Eh) bit description . . . . . . . . . . . . . .72

bit description . . . . . . . . . . . . . . . . . . . . . . . . .73

(address 10h) bit description . . . . . . . . . . . . . .73

(address 11h) bit description . . . . . . . . . . . . . .73

(address 12h) bit description . . . . . . . . . . . . . .73

(address 13h) bit description . . . . . . . . . . . . . .73

(address 14h) bit description . . . . . . . . . . . . . .73

(address 15h) bit description . . . . . . . . . . . . . .73

(address 16h) bit description . . . . . . . . . . . . . .73

(address 17h) bit description . . . . . . . . . . . . . .74

bit description . . . . . . . . . . . . . . . . . . . . . . . . .74

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .74

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

(address 1Bh) bit description . . . . . . . . . . . . . .75

(address 1Ch) bit description . . . . . . . . . . . . . .75

(address 1Dh) bit description . . . . . . . . . . . . . .75

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 6 December 2010

Table 139. DBG_CNTRL register (address 1Eh)

Table 140. PAGE_ADDRESS register (address 1Fh)

Table 141. Counter source . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 142. Code group synchronization state machine . . 76

Table 143. Page 6 register allocation map . . . . . . . . . . . . 77

Table 144. LN0_CFG_0 register (address 00h) bit

Table 145. LN0_CFG_1 register (address 01h) bit

Table 146. LN0_CFG_2 register (address 02h) bit

Table 147. LN0_CFG_3 register (address 03h) bit

Table 148. LN0_CFG_4 register (address 04h) bit

Table 149. LN0_CFG_5 register (address 05h) bit

Table 150. LN0_CFG_6 register (address 06h) bit

Table 151. LN0_CFG_7 register (address 07h) bit

Table 152. LN0_CFG_8 register (address 08h) bit

Table 153. LN0_CFG_9 register (address 09h) bit

Table 154. LN0_CFG_10 register (address 0Ah) bit

Table 155. LN0_CFG_11 register (address 0Bh) bit

Table 156. LN0_CFG_12 register (address 0Ch) bit

Table 157. LN0_CFG_13 register (address 0Dh) bit

Table 158. LN1_CFG_0 register (address 10h) bit

Table 159. LN1_CFG_1 register (address 11h) bit

Table 160. LN1_CFG_2 register (address 12h) bit

Table 161. LN1_CFG_3 register (address 13h) bit

Table 162. LN1_CFG_4 register (address 14h) bit

Table 163. LN1_CFG_5 register (address 15h) bit

Table 164. LN1_CFG_6 register (address 16h) bit

Table 165. LN1_CFG_7 register (address 17h) bit

2×, 4× or 8× interpolating DAC with JESD204A

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

DAC1208D750

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dac1208d750 NXP Semiconductors, dac1208d750 Datasheet - Page 96

dac1208d750

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