dac1208d750 NXP Semiconductors, dac1208d750 Datasheet - Page 12

• Manufacturer Part Number: dac1208d750
• Description: Dac1208d750 Dual 12-bit Dac; Up To 750 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1208D750
Product data sheet
Fig 3.
The descrambler can be enabled/disabled
JESD204A receiver
10.2 JESD204A receiver
This device is MCDA-ML compliant, offering inter-lane alignment between several
devices. Samples alignment between devices is maintained up to output level because of
an NXP proprietary mechanism. One device is configured as the master and all the others
are configured as slaves. These will automatically align their output samples to the master
ones. Therefore, a system with several DAC1208D750s can produce data with a
guaranteed alignment of less than 1 DAC output clock period.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN. This provides a full-scale output current of up to 20 mA. An internal
reference is available for the reference current which is externally adjustable using pin
VIRES.
The DAC1208D750 must be configured before operating. Therefore, it features an SPI
slave interface to access internal registers. Some of these registers also provide
information about the JESD204A interface status.
The DAC1208D750 requires both supplies of 3.3 V and 1.8 V. The 1.8 V supply has
separate digital and analog power supply pins. The clock input is LVDS compliant.
The JEDEC204A defines the following parameters:
The DAC1208D750 supports both LMF = 421 and LMF = 211. The current setting is
configurable via the SPI registers interface.
The complete Digital Layer Processing (DLP) adds a variable delay on each lane path.
This is mainly because of the inter-lane alignment.
Table 6.
[1]
[2]
Symbol Parameter
t
d
D = guaranteed by design.
Frame clock cycle.
delay time
Digital Layer Processing Latency
L is the number of lanes per link
M is the number of converters per device
F is the number of bytes per frame clock period
All information provided in this document is subject to legal disclaimers.
Conditions
digital layer processing
delay
Rev. 2 — 6 December 2010
IOUTAP/IOUTBP
IOUTAN/IOUTBN
2×, 4× or 8× interpolating DAC with JESD204A
Test
D
R L
[1]
Min
13
R L
DAC1208D750
Typ
-
© NXP B.V. 2010. All rights reserved.
Max
28
Unit
cycle
12 of 98
[2]