dac1208d750 NXP Semiconductors, dac1208d750 Datasheet
dac1208d750
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dac1208d750 Summary of contents
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... PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum number of lanes of the DAC1208D750 is 4 and its maximum serial data rate is 3.125 Gbps. The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output clock period between several DAC devices ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 Fully compatible SPI port Industrial temperature range from −40 °C to +85 °C Integrated PLL can be bypassed ...
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... CLKINN Fig 1. Block diagram SCS_N SCLK NCO 32-bit frequency setting 16-bit phase adjustment cos FIR 1 FIR 2 FIR 3 2 × 2 × 2 × SINGLE SIDE DAC1208D750HN BAND MODULATOR FIR 1 FIR 2 FIR 3 2 × 2 × 2 × MULTI-DAC SYNCHRONIZATION RESET_N MDS_P 10-BIT AUXAP AUX. OFFSET ...
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... I/O DAC biasing resistor 9 I/O band gap input/output voltage 10 P analog supply voltage 1 analog supply voltage 1.8 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A 48 n. DDD(1V8) 46 MDS_N 45 MDS_P 44 V DDA(1V8) ...
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... P digital supply voltage 1 not connected 49 P digital supply voltage 1 synchronization request to transmitter, complementary output 51 O synchronization request to transmitter All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 Conditions Min −0.5 −0.5 −0.5 −55 −40 −40 Conditions ...
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... Sleep mode maximum input rate [3] range: CLK+ or CLK− < [4] gpd All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A ° amb L [1] Test ...
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... GND and MDS_N or MDS_P between pins GND and MDS_N or MDS_P All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A ° amb L [1] ...
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... Table 21 to Table 24) reg value = F8000000h (see Table 21 to Table 24) All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A ° amb L [1] Test Min Typ ...
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... Msps 153 MHz 1 carrier MHz 2 carriers MHz 4 carriers MHz All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A ° amb L [1] ...
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... Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It reflects the delay required by DAC1208D750 to lock to a JESD204A stream. It supposes that the TX is already transmitting K28.5 characters in error-free conditions. CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80 Ω and 120 Ω (see ...
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... The DAC1208D750 must be configured before operating. Therefore, it features an SPI slave interface to access internal registers. Some of these registers also provide information about the JESD204A interface status. The DAC1208D750 requires both supplies of 3.3 V and 1.8 V. The 1.8 V supply has separate digital and analog power supply pins. The clock input is LVDS compliant. 10.2 JESD204A receiver The descrambler can be enabled/disabled Fig 3 ...
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... As stated in JESD204A, the transmitter and the receiver first have to synchronize. This is achieved through SYNC_OUT signals and a sync pattern (K28.5 symbol). The receiver (i.e. DAC1208D750) first drives its SYNC_OUT outputs. The sync pattern is continuously sent until the receiver deasserts the SYNC_OUT signal. DAC1208D750 ...
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... The SYNC_OUT signal is also used during normal operation by the DAC1208D750 to request a link reinitialization. This occurs when the 10b/8b module loses synchronization. The SYNC_OUT signal conforms to LVDS signaling. Its common-mode voltage and its ...
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... ILA_BUF_ERR_LN0 to ILA_BUF_ERR_LN3 10.2.5.2 Multi-device operation DAC1208D750 implements a multi-device inter-lane alignment that guarantees a skew of less than one output period between them. Two modes are available: master/slave and all slave. Both make use of the MDS_P and MDS_N pins ...
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... DAC1208D750 Product data sheet ref_A LANES DIG SYNC~ Multi-Device Synchronization (MDS) implementation All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A mds_A_out MDS_A COMP mds_A I BUFFER Q CLK ...
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... DIG SYNC_0 ref_A DIG SYNC_1 ref_A DIG SYNC_2 Master-slave mode All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A mds_out COMP mds_in I BUFFER Q CLK MGMT DAC mds_out COMP ...
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... PH03 slave 2 clock Clock skew case 1: Master is the farthest All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A TDAC PH01 001aal072 = PH01 − PH03, where PH0x represents the 1 ...
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... TDAC − δ mds 1 < 1333 ps − (266 ps) mds < 987 ps mds < 14.8 cm mds All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 TDAC 001aal071 = PH03 − PH01. © NXP B.V. 2010. All rights reserved ...
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... SYNC_1 SYNC_2 dT MDS < TDAC − δt, where δt is the clock skew considered close to DAC pins. All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A mds_out ref_A COMP mds_in I DIG ...
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... NXP Semiconductors 10.2.6 Frame assembly DAC1208D750 supports only / which means that every frame clock period carries one byte per lane. Frame assembly combines the octet of lane_0 with the four MSB bits of lane_1 and reassembles the original 12-bit sample. The same is done for lane_2 and lane_3 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A FRAME CLOCK 312.5 MHz /F octet ON/OFF byte 0 S7 D11 S6 D10 S5 D09 S4 D08 S3 ...
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... NXP Semiconductors 10.3 Serial Peripheral Interface (SPI) 10.3.1 Protocol description The DAC1208D750 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both Write mode and Read mode. ...
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... SCLK pulse width SCS_N set-up time SCS_N hold time SDIO set-up time SDIO hold time RESET_N pulse width All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A t w(SCLK) Table 9. Min Typ ...
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... The DAC1208D750 has one differential clock input, CLKINN/CLKINP. Fig 15. LVDS clock configuration Fig 16. Interfacing CML to LVDS The DAC1208D750 can operate with a clock frequency up to 312.5 MHz 750 MHz if the internal PLL is bypassed. The clock input can be LVDS (see also be interfaced with CML (see clock domain to another one is handled by Clock Domain Interface (CDI) logic ...
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... H(39) - H(38 H(37) 1521 - H(36 −2315 H(35) - H(34 H(33) 3671 - H(32 −6642 H(31) - H(30 H(29) 20756 - - 32768 - All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A Third interpolation filter Upper Value Lower −2 H(23) H(1) H(22) 0 H(2) H(21) 17 H(3) H(20) 0 H(4) −75 H(19) H(5) H(18) 0 H(6) H(17) 238 H(7) H(16) 0 H(8) −660 H(15) - H(14 H(13) ...
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... -------------- 5 2 Table 11. All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A = 640 Msps and the default phase is 0°. s (1) (2) © NXP B.V. 2010. All rights reserved ...
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... ⎝ ⎠ 4095 map”) defines whether the DAC1208D750 operates with a binary input shows the output current as a function of the input data, when I DAC transfer function I13/Q13 to I0/Q0 Binary Two’s complement 0000 0000 0000 1000 0000 0000 ... ...
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... NXP Semiconductors 10.9 Full-scale current 10.9.1 Regulation The DAC1208D750 reference circuitry integrates an internal band gap reference voltage which delivers a 1.25 V reference to the GAPOUT pin recommended to decouple pin GAPOUT using a 100 nF capacitor. The reference current is generated via an external resistor of 909 Ω connected to pin VIRES. A control amplifier sets the appropriate full-scale current (I ...
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... The coding of the fine gain adjustment is two’s complement. 10.10 Digital offset correction When the DAC1208D750 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common-mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. ...
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... Analog output The DAC1208D750 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a load resistor R ...
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... NXP Semiconductors 10.12 Auxiliary DACs The DAC1208D750 integrates two auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a 10-bit resolution and are current sources (referenced to ground AUX ...
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... The use of a differentially-coupled transformer output provides optimum distortion performance (see electrical isolation. Fig 19 The DAC1208D750 can operate configuration recommended to connect the center tap of the transformer Ω resistor connected to the 3.3 V analog power supply in order to adjust the DC common-mode to approximately 2.7 V (see Fig 20 ...
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... DC interface to an Analog Quadrature Modulator (AQM) When the system operation requires to keep the DC component of the spectrum, the DAC1208D750 must use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC ...
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... IOUTnP/IOUTnN; V o(cm) (2) BBP/BBN 3 i(cm) auxiliary DACs All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A AQM (V i(cm) (2) BBP BBN 698 Ω 698 Ω 51.1 Ω 51.1 Ω ...
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... NXP Semiconductors 10.13.3 AC interface to an Analog Quadrature Modulator (AQM) When the AQM common-mode voltage is close to ground, the DAC1208D750 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 0.5 V when using auxiliary DACs. i(cm) Fig 25. Example interface connection to an AQM with a V ...
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... Configuration interface 10.15.1 Register description DAC1208D750 implements indirect addressing using a page access method. The page-address is located at address 0x1F and is by default 0x00, which selects page 0 as default page. For example, to access registers which configure the JESDRX, one must first activate page 4 by writing 0x04 to the page-address 0x1F. ...
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Page 0 allocation map description Table 17. Page 0 register allocation map Address Register name R/W Bit definition b7 0 00h COMMON R/W SPI_3W 1 01h TXCFG R/W NCO_EN 2 02h PLLCFG R/W PLL_PD 3 03h FREQNCO_LSB R/W 4 ...
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Table 17. Page 0 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch DAC_B_AUX_MSB R/W 29 1Dh DAC_B_AUX_LSB R/W AUX_B_PD 31 1Fh PAGE_ADDRESS R AUX_B[9: ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... NCO frequency setting Access Value Description R/W 66h upper intermediate 8 bits for the NCO frequency setting All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Value Description R/W 3h most significant 2 bits for the DAC A gain setting for coarse adjustment R/W 00h most significant 6 bits for the DAC A offset All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... R/W noise shaper 0 disabled 1 enabled Access Value Description R/W 3h bias current control (see Access Value Description R/W 3h bias current control (see All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 Table 46) Table 46) © NXP B.V. 2010. All rights reserved ...
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... R/W 0h lower 2 bits for auxiliary DAC A Access Value Description R/W 80h most significant 8 bits for auxiliary DAC B All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 Table 46) Table 46) Table 46) Table 46) © NXP B.V. 2010. All rights reserved ...
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... Value R R/W 0h Access Value R/W 0h Bias current control table All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 Description auxiliary DAC B power on off lower 2 bits for auxiliary DAC B Description page address Deviation from nominal current −30 % ... ... ...
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Page 1 allocation map description Table 47. Page 1 register allocation map Address Register name R/W Bit definition b7 0 00h MDS_MAIN R/W MDS_EQCHECK[1:0] 1 01h MDS_WIN_PERIOD_A R/W 2 02h MDS_WIN_PERIOD_B R/W 3 03h MDS_MISCCNTRL0 R 04h ...
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... MDS function 1 enable MDS function Access Value Description R/W 80h determines MDS window LOW-time Access Value Description R/W 40h determines MDS window HIGH-time All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... LOW R/W lockout detector soft reset 0 mds_lockout in use 1 mds_lockout forced LOW R/W lock detector soft reset 0 mds_lock in use 1 mds_lock forced LOW All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... R evaluation logic has detected equal condition 0 false 1 true R evaluation logic active 0 false 1 true All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... MDS pre-run phase active flag 0 false 1 true R MDS lockout detected flag 0 false 1 true R MDS lock flag 0 false 1 true Access Value Description R/W 0h page address All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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Page 2 allocation map description Table 59. Page 2 register allocation map Address Register name R/W Bit definition b7 0 00h MAINCONTROL R 03h JCLK_CNTRL R/W SR_CDI 4 04h RST_EXT_FCLK R/W 5 05h RST_EXT_DCLK R/W 6 06h ...
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... R/W f polarity clk 0 no action 1 invert polarity R/W f clock source clk dclk × dclk 10 dclk_div2; running 11 dclk_div2; reset dclk_div2 divider All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Value Description R/W 4h set synchronization transmitter common-mode level (see R/W 3h set synchronization transmitter output level swing (see All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 clk /DCSMU_PREDIVIDER[7:0]) clk /DCSMU_PREDIVIDER[7:0]) clk /DCSMU_PREDIVIDER[7:0]) clk Table 76) Table 77) © NXP B.V. 2010. All rights reserved. ...
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... DAC core version Access Value Description R 02h digital version Access Value Description R 02h analog deserializer version Access Value Description R/W 0h page address All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... SYNC common-mode voltage adjustment SET_SYNC_VCOM[2:0] 111 110 101 100 011 010 001 000 SYNC swing voltage adjustment SET_SYNC_LEVEL[2:0] 111 110 101 100 011 010 001 000 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 V (V) com 1.40 1.36 1.31 1.26 1.21 1.16 1.12 1.07 1.02 0.97 0.92 0.87 0.82 0.78 0.73 0.68 V (V) com 1 ...
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Page 4 allocation map description Table 78. Page 4 register allocation map Address Register name R/W Bit definition 00h SR_DLP_0 R/W SR_SWA_ SR_SWA_ LN3 1 01h SR_DLP_1 R/W SR_CNTRL SR_CNTRL _LN3 2 02h FORCE_LOCK R/W FORCE_ ...
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Table 78. Page 4 register allocation map …continued Address Register name R/W Bit definition 12h INIT_SCR_ R/W - S7T1_LN0 19 13h INIT_SCR_ R/W S15T8_LN1 20 14h INIT_SCR_ R/W - S7T1_LN1 21 15h INIT_SCR_ R/W S15T8_LN2 22 16h ...
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... R/W lane 0 lock mode 0 automatic lock sync_word_alignment lane 0 1 manual lock sync_word_alignment lane 0 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... R/W lane 2 sampling mode 0 din_ca_ln2 sampled at falling edge f10_ln2 1 din_ca_ln2 sampled at rising edge f10_ln2 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... R/W lane 0 scrambling mode 0 scrambling lane 0 depends on lock_ln0 and en_scr 1 scrambling lane 0 depends on man_scr_ln0 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Access Value Description R/W 0h indicates alignment data-delay for lane 1 [1..15] R/W 0h indicates alignment data-delay for lane 0 [1..15] All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... R/W lane 1 data polarity 0 no action 1 invert all data bits of lane 1] R/W lane 0 data polarity 0 no action 1 invert all data bits of lane 0 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... R/W lane 0 scrambler reset 0 no action 1 soft_reset scrambler of lane 0 Access Value Description R/W 00h initialization value for lane 0 descrambler bits s15 : s8 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... ILA buffer pointer Access Value Description R/W 8h initialization value for lane 3 ILA buffer pointer R/W 8h initialization value for lane 2 ILA buffer pointer All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... R/W lane 0, ila-buffer out-of-range check 0 no action 1 lane 0 ila-buffer out-of-range_error will activate reinitialization All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... K28.5 /K/ symbols R/W lane 0, resync over link 0 no action 1 lane 0 controller checks for K28.5 /K/ symbols Access Value Description R/W 0h page_address All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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Page 5 allocation map description Table 108. Page 5 register allocation map Address Register name R/W Bit definition 00h ILA_MON_1_0 R 1 01h ILA_MON_3_2 R 2 02h ILA_BUF_ERR 03h CA_MON R CA_MON_LN3[1:0] 4 ...
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Table 108. Page 5 register allocation map …continued Address Register name R/W Bit definition 11h FLAG_CNT_ R MSB_LN0 18 12h FLAG_CNT_LSB R _LN1 19 13h FLAG_CNT_ R MSB_LN1 20 14h FLAG_CNT_LSB R _LN2 21 15h FLAG_CNT_ R ...
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... R - clock alignment phase monitor lane clock alignment phase monitor lane clock alignment phase monitor lane 0 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... K28_7 /F/ symbols found in lane K28_5 /K/ symbols found in lane K28_4 /Q/ symbols found in lane K28_3 /A/ symbols found in lane K28_0 /R/ symbols found in lane 2 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... R - monitor cs_state fsm lane 0 (see Access Value Description R/W 0 reset ILA_BUF_ERR_LNn flags All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 Table 142) Table 142) Table 142) Table 142) © NXP B.V. 2010. All rights reserved ...
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... MSBs of flag_counter lane 1 Access Value Description R - LSBs of flag_counter lane 2 Access Value Description R - MSBs of flag_counter lane 2 Access Value Description R - LSBs of flag_counter lane 3 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... K28_5 in ln<x> affects i_ln<x> R/W K28_3 interrupt 0 no action 1 detection K28_3 in ln<x> affects i_ln<x> R/W miscellaneous interrupt 0 no action 1 detection depends on intr_misc_ena (see All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 Table 124) © NXP B.V. 2010. All rights reserved ...
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... K28_x monitor flags for lane 2 R/W 0 reset K28_x monitor flags for lane 1 R/W 0 reset K28_x monitor flags for lane 0 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 Table 141) Table 141) Table 141) Table 141) © ...
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... K28_0 (/R/) symbol found Definition looking for K28_5 (/K/) symbol four consecutive K28_5 (/K/) symbols have been received code group synchronization achieved not applicable All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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Page 6 allocation map description Table 143. Page 6 register allocation map Address Register name R/W Bit definition b7 0 00h LN0_CFG_0 R 1 01h LN0_CFG_1 02h LN0_CFG_2 03h LN0_CFG_3 R LN0_SCR 4 ...
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Table 143. Page 6 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN1_CFG_12 R 29 1Dh LN1_CFG_13 R 31 1Fh PAGE_ADDRESS R undefined at power-up or after reset ...
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... Access Value Description R - number of converters per device minus 1 Access Value Description R - number of control bits R - converter resolution minus 1 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Access Value Description R - lane 0 checksum Access Value Description R - lane 1 device ID Access Value Description R - lane 1 bank ID Access Value Description R - lane 1 lane ID All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Value Description R - number of samples per converter per frame cycle minus 1 Access Value Description R - high density R - number of control words per frame cycle All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Access Value Description R - lane 1 reserved field Access Value Description R - lane 1 reserved field Access Value Description R - lane 1 checksum Access Value Description R/W 0h page_address All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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Page 7 allocation map description Table 173. Page 7 register allocation map Address Register name R/W Bit definition b7 0 00h LN2_CFG_0 R 1 01h LN2_CFG_1 02h LN2_CFG_2 03h LN2_CFG_3 R LN2_SCR 4 ...
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Table 173. Page 7 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN3_CFG_12 R 29 1Dh LN3_CFG_13 R 31 1Fh PAGE_ADDRESS R undefined at power-up or after reset ...
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... Access Value Description R - number of converters per device minus 1 Access Value Description R - number of control bits R - converter resolution minus 1 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Access Value Description R - lane 2 checksum Access Value Description R - lane 3 device ID Access Value Description R - lane 3 bank ID Access Value Description R - lane 3 lane ID All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Value Description R - number of samples per converter per frame cycle minus 1 Access Value Description R - high density R - number of control words per frame cycle All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Access Value Description R - lane 3 reserved field Access Value Description R - lane 3 reserved field Access Value Description R - lane 3 checksum Access Value Description R/W 0h page_address All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... 9.1 7.25 9.1 7.25 9.0 7.10 9.0 7.10 0.5 7.5 7.5 8.9 6.95 8.9 6.95 References JEDEC JEITA - - - - - - All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 2×, 4× or 8× interpolating DAC with JESD204A detail 0.5 0.4 0.1 0.05 0.05 0.1 0.3 European projection SOT804 ...
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... Spurious Free Dynamic Range Serial Peripheral Interface Time Division-Synchronous Code Division Multiple Access Wideband Code Division Multiple Access Worldwide interoperability for Microwave Access All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 13. Revision history Table 204. Revision history Document ID Release date DAC1208D750 v.2 20101206 • Modifications: Data sheet status changed from Objective to Product. • Text and drawings updated throughout entire data sheet. • Values in • Section 10.2.2 “Sync and word align” • ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors’ product specifications. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Table 57. MDS_STATUS1 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 58. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 59. Page 2 register allocation map . . . . . . . . . . . . 51 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 continued >> © NXP B.V. 2010. All rights reserved ...
Page 95
... Table 111. ILA_BUF_ERR register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 112. CA_MON register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 113. DEC_FLAGS register (address 04h) bit All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 continued >> © NXP B.V. 2010. All rights reserved ...
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... Table 163. LN1_CFG_5 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 164. LN1_CFG_6 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 165. LN1_CFG_7 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 continued >> © NXP B.V. 2010. All rights reserved ...
Page 97
... Table 201. LN3_CFG_13 register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 202. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 203. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 204. Revision history . . . . . . . . . . . . . . . . . . . . . . . 91 All information provided in this document is subject to legal disclaimers. Rev. 2 — 6 December 2010 DAC1208D750 © NXP B.V. 2010. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 6 December 2010 Document identifier: DAC1208D750 ...