dac1208d750 NXP Semiconductors, dac1208d750 Datasheet - Page 11

• Manufacturer Part Number: dac1208d750
• Description: Dac1208d750 Dual 12-bit Dac; Up To 750 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 5.
V
+85
maximum sample rate; PLL off unless otherwise specified.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
10. Application information
DAC1208D750
Product data sheet
Symbol
NSD
DDA(1V8)
°
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It
reflects the delay required by DAC1208D750 to lock to a JESD204A stream. It supposes that the TX is already transmitting K28.5
characters in error-free conditions.
CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80 Ω and 120 Ω (see
Figure
|V
and the inductance between the receiver and the driver circuit ground voltage.
Vin_p and Vin_n inputs are differential CML inputs. They are terminated internally to V
SYNC_OUTP/SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80 Ω
and 120 Ω.
Optimum performances at high sampling rate (> 650 Msps) will be achieved with V
IMD3 rejection with −6 dBFS/tone.
C; typical values measured at V
gpd
| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
= V
15) should be connected across the pins.
Characteristics
DDD
10.1 General description
Parameter
noise spectral density
= 1.7 V to 1.9 V; V
The DAC1208D750 is a dual 12-bit DAC operating up to 750 Msps. With a maximum input
data rate of up to 312.5 Msps and a maximum output sampling rate of 750 Msps, the
DAC1208D750 allows more flexibility for wide bandwidth and multi-carrier systems.
Combined with its quadrature modulator and 32-bit NCO, the DAC1208D750 simplifies
the frequency selection of the system. This is also possible because of the 2×, 4× or 8×
interpolation filters which remove undesired images.
DAC1208D750 supports the following JESD204A key features:
DAC1208D750 can be interfaced with any logic device that features high-speed SERDES
functionality. This macro is now widely available in FPGA from different vendors.
Standalone SERDES ICs can also be used.
To enhance the intrinsic board layout simplification of the JESD204A standard, NXP
includes polarity swapping for each of the lanes and additionally offers lane swapping.
Each physical lane can be configured logically as lane0, lane1, lane2 or lane3.
•
•
•
•
•
•
•
…continued
10-bit/8-bit decoding
Code group synchronization
inter-lane alignment
1 + x
Character replacement
TX/RX synchronization management via SYNC signals
Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device
14
DDA(3V3)
DDA(1V8)
+ x
Conditions
f
4× interpolation;
f
15
s
o
All information provided in this document is subject to legal disclaimers.
= 737.28 Msps;
= 153.6 MHz at 0 dBFS
scrambling polynomial
= 3.13 V to 3.47 V; AGND and GND are shorted together; T
= V
DDD
Rev. 2 — 6 December 2010
= 1.8 V; V
DDA(3V3)
2×, 4× or 8× interpolating DAC with JESD204A
= 3.3 V; T
Test
I
[1]
DDA(1V8)
tt
[7]
amb
via 50 Ω (see
Min
-
= +25
= 1.8 V ± 2 %.
DAC1208D750
°
C; R
Typ
−154
Figure
L
= 50
4).
Max
-
Ω
© NXP B.V. 2010. All rights reserved.
amb
; I
O(fs)
=
−
40
= 20 mA;
°
Unit
dBm/Hz
C to
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