pca9665 NXP Semiconductors, pca9665 Datasheet - Page 64

• Manufacturer Part Number: pca9665
• Description: Fm+ Parallel Bus To I2c-bus Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9665_2
Product data sheet
Fig 25. Bus timing diagram; Buffered Slave Transmitter mode
Fig 26. Bus timing diagram; Buffered Slave Receiver mode
Fig 27. Bus timing diagram; Software Reset Call
(1) As defined in I2CADR register.
(2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0]
(1) As defined in I2CADR register.
(2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0]
SDA
condition
SCL
INT
START
External master receiver reads data from PCA9665.
Slave PCA9665 is written to by external master transmitter.
SDA
condition
SCL
INT
START
SDA
condition
SCL
INT
START
from slave PCA9665
from slave PCA9665
7-bit SWRST
Call address
from slave PCA9665
7-bit address
R/W = 0
7-bit address
R/W = 0
R/W = 1
(1)
ACK
(1)
interrupt
ACK
ACK
interrupt
interrupt
first byte = 0xA5
Rev. 02 — 7 December 2006
first byte
first byte
(2)
(2)
ACK
ACK
ACK
second byte = 0x5A
from master receiver
n byte
n byte
Fm+ parallel bus to I
68).
(2)
68).
(2)
ACK
no ACK
ACK
interrupt
interrupt
PCA9665
STOP
condition
© NXP B.V. 2006. All rights reserved.
2
002aab269
(after STOP)
STOP
condition
C-bus controller
002aab270
interrupt
STOP
condition
(after STOP)
002aab488
interrupt
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