pca9665 NXP Semiconductors, pca9665 Datasheet - Page 36

• Manufacturer Part Number: pca9665
• Description: Fm+ Parallel Bus To I2c-bus Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9665_2
Product data sheet
8.4.2 Master Receiver Buffered mode
In the Master Receiver Buffered mode, a number of data bytes are received from a slave
transmitter several bytes at a time (see
Master Transmitter Byte mode.
The Master Receiver Buffered mode may now be entered by setting the STA bit. The
I
as the bus becomes free. When a START condition is transmitted, the Serial Interrupt flag
(SI) is set, the Interrupt line (INT) goes LOW and the status code in the status register
(I2CSTA) will be 08h. This status code must be used to vector to an interrupt service
routine that loads I2CDAT with the slave address and the data direction bit (SLA+R). The
byte count register (I2CCOUNT) needs to be programmed with the number of bytes that
need to be received in a single sequence (BC[6:0]). LB bit is programmed with logic 0 if
the last received byte needs to be acknowledged (read operation still ongoing) or with
logic 1 if the last received byte needs to be not acknowledged (read operation ends so the
PCA9665 can issue a STOP or Re-START condition). A write to I2CCON resets the SI bit,
clears the Interrupt (INT goes HIGH) and allows the serial transfer to continue.
When the slave address and the data direction bit have been transmitted and all the data
bytes have been received, the Serial Interrupt flag (SI) is set again, the Interrupt line (INT)
goes LOW again and I2CSTA is loaded with the following possible codes:
The appropriate action to be taken for each of these status codes is detailed in
ENSIO is not affected by the serial transfer and is not referred to in
After a repeated START condition (state 10h), the PCA9665 may switch to the Master
Transmitter mode by loading I2CDAT with SLA+W.
Remark: A master should not transmit its own slave address.
2
C-bus state machine will first test the I
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48h if a no acknowledgment bit (NACK) has been received for the slave address with
direction bit
50h when all the bytes have been received and an acknowledgement bit (ACK) has
been returned for all the bytes
58h when all the bytes have been received and an acknowledgement bit (ACK) has
been returned for all the bytes except the last one
38h if the PCA9665 lost the arbitration
B0h if the PCA9665 lost the arbitration and is addressed as a slave transmitter (slave
mode enabled with AA = 1)
68h if the PCA9665 lost the arbitration and is addressed as a slave receiver (slave
mode enabled with AA = 1)
D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a
General Call sequence (slave mode enabled with AA = 1 and General Call address
enabled with GC = 1 in I2CADR register).
Rev. 02 — 7 December 2006
Figure
2
C-bus and generate a START condition as soon
12). The transfer is initialized as in the
Fm+ parallel bus to I
Table
PCA9665
© NXP B.V. 2006. All rights reserved.
2
C-bus controller
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Table
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