pca9665 NXP Semiconductors, pca9665 Datasheet - Page 51

• Manufacturer Part Number: pca9665
• Description: Fm+ Parallel Bus To I2c-bus Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9665_2
Product data sheet
8.6 I2CCOUNT register
10. Program I2CCOUNT = C0h (64 bytes and Last byte is not acknowledged).
11. Program I2CCON with STA = STO = SI = 0, MODE = 1.
12. The PCA9665 reads 64 bytes and does not acknowledge the last byte.
13. The microcontroller reads the 64 bytes from the PCA9665.
14. Program I2CCON with SI = STA = 0, ST0 = 1, MODE = X.
When a write to the I2CCOUNT register is requested, the buffer pointer is reset and points
at the first byte. Loading of the data in the I2CDAT buffer then starts at the first byte.
Once an operation has been performed (SI = 1 and an interrupt is generated), the
I2CCOUNT register contains the number of bytes that have been received (Receiver
mode) or the number of bytes that have been sent (Transmitter mode). See
more information.
In Buffered Transmitter mode, the first byte that is sent to the I
byte that has been loaded in the I2CDAT buffer.
5. Program I2CCOUNT = 40h (64 bytes to read and Last byte acknowledged).
6. Load I2CDAT with A1h (I
7. Program I2CCON with STA = 1, SI = 0, MODE = 1.
8. Program I2CCON with STA = STO = SI = 0, MODE = 1.
9. The microcontroller reads the 64 data bytes from the PCA9665.
– the SCL line is held LOW by the PCA9665 after the 2 bytes have been sent
– the PCA9665 sends an Interrupt, sets SI = 1 and updates I2CSTA register
– I2CSTA reads 28h
– the PCA9665 sends a ReSTART command
– an interrupt is asserted and the I2CSTA register is updated
– the I2CSTA register reads 10h
– address A1h is sent followed by a read of 64 data bytes
– the last data byte is acknowledged
– the SCL line is held LOW by the PCA9665 after the data is read
– the PCA9665 sends an interrupt and updates I2CSTA register
– I2CSTA reads 50h
– the PCA9665 sends an Interrupt and updates I2CSTA register
– the I2CSTA reads 58h
– the SCL line is held LOW by the PCA9665
– the slave should release the SDA line
– the PCA9665 sends a STOP condition
– no interrupt is generated by the PCA9665
– the I2CSTA register contains F8h
Rev. 02 — 7 December 2006
2
C-bus slave address and Read command).
Fm+ parallel bus to I
2
C-bus is always the first
PCA9665
© NXP B.V. 2006. All rights reserved.
2
C-bus controller
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