pca9665 NXP Semiconductors, pca9665 Datasheet - Page 61

• Manufacturer Part Number: pca9665
• Description: Fm+ Parallel Bus To I2c-bus Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9665_2
Product data sheet
Fig 18. Parallel Software Reset sequence
Fig 19. Bus timing diagram; Unbuffered Master Transmitter mode
internal
D[7:0]
A[1:0]
signal
Master PCA9665 writes data to slave transmitter.
reset
WR
SDA
condition
SCL
INT
START
from slave receiver
8.11 Reset
8.12 I
Indirect Register pointer
7-bit address
I2CPRESET register selected
Reset of the PCA9665 to its default state can be performed in 2 different ways:
The diagrams
PCA9665 in master/slave functions.
access to INDPTR
2
•
•
C-bus timing diagrams, Unbuffered mode
R/W = 0
By holding the RESET pin LOW for a minimum of t
By using the Parallel Software Reset sequence as described in
00
following byte is ignored
05h
and reset is aborted.
ACK
If D[7:0]
(Figure 19
interrupt
A5h,
Rev. 02 — 7 December 2006
through
first byte
SWRST data byte 1
SWRST Data 2 = 5Ah, PCA9665
If D[7:0]
If SWRST Data 1 = A5h and
A5h
is reset to its default state.
Figure
access to the INDIRECT
ACK
5Ah, reset is aborted.
Indirect Data field
interrupt
22) illustrate typical timing diagrams for the
10
Fm+ parallel bus to I
n byte
SWRST data byte 2
w(rst)
ACK
5Ah
.
interrupt
Figure
PCA9665
© NXP B.V. 2006. All rights reserved.
2
002aab031
STOP
condition
C-bus controller
18.
002aab966
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