kad5514p Kenet Inc., kad5514p Datasheet - Page 23

• Manufacturer Part Number: kad5514p
• Description: 14-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incremented
or decremented value back to the same register.
Address 0x22: gain_coarse
Address 0x23: gain_medium
Address 0x24: gain_fine
Gain of each ADC core can be adjusted in coarse,
medium and fine steps. Coarse gain is a 4-bit adjust-
ment while medium and fine are 8-bit.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incremented
or decremented value back to the same register.
KAD5514P
Nominal Step Size
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Parameter
Steps
Table 8. Coarse Gain Adjustment
Table 7. Offset Adjustments
0x22[3:0]
1100
1000
0100
0000
0001
0010
0011
+133LSB (+47mV)
1.04LSB (0.37mV)
-133LSB (-47mV)
Coarse Offset
0.0LSB (0.0mV)
0x20[7:0]
255
Nominal Coarse
Gain Adjust
-1.4%
-2.8%
-4.2%
4.2%
2.8%
1.4%
0.0%
0.04LSB (0.014mV)
+5LSB (+1.75mV)
-5LSB (-1.75mV)
Fine Offset
0x21[7:0]
0.0LSB
255
Preliminary
Address 0x25: modes
Two distinct reduced power modes can be selected.
By default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to Nap/Sleep
section). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function
when driven from the pin. This register is not changed
by a Soft Reset.
Global Device Configuration/Control
Address 0x71: phase_slip
When using the clock divider, it’s not possible to deter-
mine the synchronization of the incoming and divided
clock phases. This is particularly important when multi-
ple ADCs are used in a time-interleaved system. The
phase slip feature allows the rising edge of the divided
clock to be advanced by one input clock cycle, as
shown in Figures 40 and 41. This register is self-clearing.
Nominal Step Size
Table 9. Medium and Fine Gain Adjustments
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Parameter
Steps
Table 10. Power Down Control
Value
000
001
010
100
Medium Gain
0x23[7:0]
0.016%
0.0%
+2%
256
-2%
Power Down Mode
Normal Operation
Sleep Mode
Pin Control
Nap Mode
0x25[2:0]
Fine Gain
0x24[7:0]
0.0016%
+0.2%
-0.2%
0.0%
256
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