kad5514p Kenet Inc., kad5514p Datasheet - Page 17

• Manufacturer Part Number: kad5514p
• Description: 14-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

Best performance is obtained when the analog in-
puts are driven differentially. The common-mode out-
put voltage, VCM, should be used to properly bias
the inputs as shown in Figures 28 through 30. An RF
transformer will give the best noise and distortion per-
formance for wideband and/or high intermediate
frequency (IF) inputs. Two different transformer input
schemes are shown in Figures 28 and 29.
This dual transformer scheme is used to improve com-
mon-mode rejection, which keeps the common-
mode level of the input matched to VCM. The value
of the shunt resistor should be determined based on
the desired load impedance. The differential input
resistance of the KAD5514P is 500Ω.
The SHA design uses a switched capacitor input
stage (see Figure 43), which creates current spikes
when the sampling capacitance is reconnected to
the input voltage. This causes a disturbance at the
input which must settle before the next sampling
point. Lower source impedance will result in faster
Figure 29. Transmission-line Transformer Input for High
KAD5514P
Figure 28. Transformer Input for General Purpose
Figure 27. Analog Input Range
IF Applications
Applications
Preliminary
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recom-
mended for optimal performance.
A differential amplifier, as shown in Figure 30, can be
used in applications that require dc-coupling. In this
configuration the amplifier will typically dominate the
achievable SNR and distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure
44). Driving these inputs with a high level (up to 1.8V
on each input) sine or square wave will provide the
lowest jitter performance. A transformer with 4:1 im-
pedance ratio will provide increased drive levels.
The recommended drive circuit is shown in Figure 31.
A duty range of 40% to 60% is acceptable. The clock
can be driven single-ended, but this will reduce the
edge rate and may impact SNR performance. The
clock inputs are internally self-biased to AVDD/2 to
facilitate AC coupling.
A selectable 2X frequency divider is provided in series
with the clock input. The divider can be used in the
2X mode with a sample clock equal to twice the de-
sired sample rate. This allows the use of the Phase Slip
feature, which enables synchronization of multiple
ADCs.
Figure 31. Recommended Clock drive
Figure 30. Differential Amplifier Input
Page 17
PP