kad5514p Kenet Inc., kad5514p Datasheet - Page 15

• Manufacturer Part Number: kad5514p
• Description: 14-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

Functional Description
The KAD5514P is based upon a 12-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 23). The input
voltage is captured by a Sample-Hold Amplifier (SHA)
and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively
compare the input to a series of reference charges.
Decisions made during the successive approximation
operations determine the digital code for each input
value. The converter pipeline requires six samples to
produce a result. Digital error correction is also ap-
plied, resulting in a total latency of seven and one
half clock cycles. This is evident to the user as a time
lag between the start of a conversion and the data
being available on the digital outputs.
The KAD5514P family operates by simultaneously
sampling the input signal with two ADC cores in par-
allel and summing the digital result. Since the input
signal is correlated between the two cores and noise
is not, an increase in SNR is achieved. As a result of
this architecture, indexed SPI operations must be exe-
cuted on each core in series. Refer to the Indexed
Device Configuration/Control section for more de-
tails.
KAD5514P
Figure 23. ADC Core Block Diagram
Preliminary
Power-On Calibration
The ADC performs a self-calibration at start-up. An
internal power-on-reset (POR) circuit detects the sup-
ply voltage ramps and initiates the calibration when
the analog and digital supply voltages are above a
threshold. The following conditions must be adhered
to for the power-on calibration to execute success-
fully:
A user-initiated reset can subsequently be invoked in
the event that the above conditions cannot be met
at power-up.
The SDO pin requires an external 4.7kΩ pull-up to
OVDD. If the SDO pin is pulled low externally during
power-up, calibration will not be executed properly.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high,
which starts the calibration sequence. If a subse-
quent user-initiated reset is required, the RESETN pin
should be connected to an open-drain driver with a
drive strength of less than 0.5mA.
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A frequency-stable conversion clock must be
applied to the CLKP/CLKN pins
DNC pins (especially 3, 4 and 18) must not be
pulled up or down
SDO (pin 66) must be high
RESETN (pin 25) must begin low
SPI communications must not be attempted
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