kad5612p Kenet Inc., kad5612p Datasheet

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... Digital output data is presented in selectable LVDS or CMOS formats. The KAD5612P is available in a 72- contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40 to +85°C). ...

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... KAD5612P Table of Contents Section Electrical Specifications DC Specifications AC Specifications Digital Specifications Absolute Maximum Ratings Timing Diagrams Switching Specifications Thermal Impedance ESD Pinout/Package Information Pin Descriptions Pin Configuration Typical Performance Characteristics Theory of Operation Functional Description Power-On Calibration User-Initiated Reset Analog Input Clock Input ...

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... LVDS 68 76 30MHz, -36 200mVpp signal on 3mA LVDS 405 434 134 146 Maximum Conversion Rate (per speed KAD5612P-17 KAD5612P-12 Typ Max Min Typ Max Min Typ 1.48 1.56 1.42 1.48 1.56 1.42 1.48 1000 1000 1000 1.8 1.8 1 ±2 10 -10 ±2 10 -10 ± ...

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... 10MHz 70MHz 105MHz 230MHz 400MHz 995MHz 70MHz -90 170MHz -86 10MHz 124MHz -12 1.3 KAD5612P-17 KAD5612P-12 Typ Max Min Typ Max Min ±0.7 -1 ±0.7 -1 ±1.6 ±1 170 125 65.8 66.2 65.7 66.2 65.6 64.2 66.0 64.5 65.7 66.1 65.5 66.0 65.7 65.9 65.2 63.7 65.7 64.0 65.2 65.6 10.6 10.7 10.6 10.7 10.5 10.3 10.6 10.3 10.5 10 ...

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... KAD5612P Digital Specifications Parameter Inputs Input Current High (RESETN) Input Current Low (RESETN) Input Current High (OUTMODE, NAP/SLP, CLKDIV, OUTFMT ) Input Current Low (OUTMODE, NAP/SLP, CLKDIV, OUTFMT ) Input Capacitance LVDS Outputs Differential Output Voltage Output Offset Voltage Output Rise Time Output Fall Time ...

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... KAD5612P Absolute Maximum Ratings Parameter AVDD to AVSS OVDD to OVSS AVSS to OVSS Analog Inputs to AVSS Clock Inputs to AVSS Logic Input to AVSS Logic Inputs to OVSS Operating Temperature Storage Temperature Junction Temperature 1. Exposing the device to levels in excess of the maximum ratings may cause permanent damage. Exposure to maximum conditions for extended periods may affect device reliability ...

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... KAD5612P Switching Specifications Parameter ADC Aperture Delay RMS Aperture Jitter Output Clock to Data Propagation Delay, LVDS Mode Output Clock to Data Propagation Delay, CMOS Mode Latency (Pipeline Delay) Over Voltage Recovery SPI Interface 1,2 SCLK Period SCLK Duty Cycle ( CLK ...

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... KAD5612P Pin Descriptions Pin # LVDS [LVCMOS] Name 1, 6, 19, 24, 71 AVDD 2-5, 17, 18, 28-31 DNC 7, 10-12, 72 AVSS 8, 9 BINP, BINN 13, 14 AINN, AINP 15 VCM 16 CLKDIV 20, 21 CLKP, CLKN 22 OUTMODE 23 NAPSLP 25 RESETN 26, 45, 55, 65 OVSS 27, 36, 56 OVDD 32, 33 D0N, D0P [NC, D0] 34, 35 D1N, D1P [NC, D1] ...

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... KAD5612P Pin Configuration AVDD 1 DNC 2 DNC 3 DNC 4 DNC 5 AVDD 6 AVSS 7 BINP 8 BINN 9 AVSS 10 AVSS 11 AVSS 12 AINN 13 AINP 14 VCM 15 CLKDIV 16 DNC 17 DNC 18 KAD5612 72 QFN Top View Not to Scale Figure 3. Pin Configuration 54 D8P 53 D8N 52 D7P 51 D7N 50 D6P 49 D6N 48 CLKOUTP 47 CLKOUTN 46 RLVDS 45 OVSS 44 D5P ...

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... KAD5612P Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V + -1dBFS, f ° SNR @ 125MSPS SNR @ 250MSPS 200 400 INPUT FREQUENCY (MHz) Figure 4. SNR & SFDR vs. f 100 ...

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... KAD5612P Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V + -1dBFS, f ° 450 400 350 300 250 200 150 100 100 130 SAMPLE RATE (MSPS) Figure 10. Power vs. f SAMPLE 2 1 ...

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... KAD5612P Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V + -1dBFS, f ° Ain = -1.0 dBFS -20 SNR = 64.9 dBFS SFDR = 83.2 dBc SINAD = 64.8 dBFS -40 -60 -80 -100 -120 FREQUENCY (MHz) Figure 16. Single-Tone Spectrum @ 105 MHz ...

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... KAD5612P Functional Description The KAD5612P is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 22). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. ...

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... SDO, RESETN and DNC pins must be in the proper state for the calibra- tion to successfully execute. The performance of the KAD5612P changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements ...

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... VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5612P is 1000Ω. The SHA design uses a switched capacitor input stage (see Figure 42), which creates current spikes when the sampling capacitance is reconnected to the input voltage ...

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... KAD5612P CLKDIV Pin Divide Ratio AVSS Float AVDD Table 1. CLKDIV Pin Settings The clock divider can also be controlled through the SPI port, which overrides the CLKDIV pin setting. De- tails on this are contained in the Serial Peripheral In- terface section. A delay-locked loop (DLL) generates internal clock signals for various stages within the charge pipeline ...

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... KAD5612P Power Dissipation The power dissipated by the KAD5612P is primarily dependent on the sample rate and the output modes: LVDS vs. CMOS and DDR vs. SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. The output supply dissipation changes to a lesser degree in LVDS mode, but is more strongly re- lated to the clock frequency in CMOS mode ...

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... KAD5612P Figure 33. Gray Code to Binary Conversion Mapping of the input voltage to the various data for- mats is shown in Table 5. Input Voltage –Full Scale 000000000000 –Full Scale 000000000001 + 1LSB Mid–Scale 100000000000 +Full Scale 111111111110 – 1LSB +Full Scale 111111111111 Table 5. Input Voltage to Output Code Mapping ...

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... The SPI port operates in a half duplex master/slave configuration, with the KAD5612P functioning as a slave. Multiple slave devices can interface to a single master in four-wire mode only, since the SDIO output of an unaddressed device is asserted in three wire mode ...

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... KAD5612P show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode the address is incremented for multi-byte transfers, while in LSB-first mode it’s decremented. In the default mode the MSB is R/W, which deter- mines if the data read (active high) or writ- ten ...

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... KAD5612P The default value of each register will be the result of the self-calibration after initial power-up register incremented or decremented, the user should first read the register value then write the incre- mented or decremented value back to the same register. Parameter 0x20[7:0] Coarse Offset ...

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... Address 0x73: output_mode_A The output_mode_A register controls the physical output format of the data, as well as the logical cod- ing. The KAD5612P can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA). By default, the tri-level OUTMODE pin se- lects the mode and drive level (refer to Digital Out- puts section) ...

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... KAD5612P Internal clock signals are generated by a delay- locked loop (DLL), which has a finite operating range. Table 15 shows the allowable sample rate ranges for the slow and fast settings. DLL Range MIN Slow 40 Fast 80 f Table 15. DLL Ranges The output_mode_B and config_status registers are used in conjunction to select the frequency range of the DLL clock generator ...

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... KAD5612P SPI Memory Map Addr (Hex) Parameter Name Bit 7 (MSB) 00 port_config SDO Active LSB First 01 reserved 02 burst_end 03-07 reserved 08 chip_id 09 chip_version 10 device_index_A 11-1F reserved 20 offset_coarse 21 offset_fine 22 gain_coarse 23 gain_medium 24 gain_fine 25 modes 26-5F reserved 60-6F reserved 70 skew_diff 71 phase_slip 72 clock_divide 73 output_mode_A Output Mode [2:0] 000=Pin Control 001=LVDS 2mA 010=LVDS 3mA ...

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... KAD5612P Equivalent Circuits Figure 42. Analog Inputs Figure 43. Clock Inputs Figure 44. Tri-Level Digital Inputs Figure 45. Digital Inputs Figure 46. LVDS Outputs Figure 47. CMOS Outputs Figure 48. VCM_OUT Output Layout Considerations Split Ground and Power Planes Data converters operating at high sampling frequen- cies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections ...

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... KAD5612P Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for opti- mal thermal performance. Bypass and Filtering Bulk capacitors should have low equivalent series re- sistance. Tantalum is a good choice. For best per- formance, keep ceramic bypass capacitors very close to device pins ...

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... KAD5612P Two-Tone SFDR is the ratio of the RMS value of the lowest power input tone to the RMS value of the peak spurious component, which may or may not be an IMD product. Outline Dimensions Figure 49. 72QFN Dimensions Page 27 ...

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... KAD5612P Ordering Guide The KAD5612P is compliant with EU directive 2002/95/EC regarding the Restriction of Hazardous Sub- RoHS stances (RoHS). Contact Kenet for a materials declaration for this product. Model KAD5612P-25Q72 KAD5612P-21Q72 KAD5612P-17Q72 KAD5612P-12Q72 Revision History 30-Jul-08: Rev 1 Initial Release of Production Datasheet Information provided by Kenet, Inc. (Kenet) is believed to be accurate and reliable as of the publication date. ...