kad5514p Kenet Inc., kad5514p Datasheet - Page 18

• Manufacturer Part Number: kad5514p
• Description: 14-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

The clock divider can also be controlled through the
SPI port, which overrides the CLKDIV pin setting. De-
tails on this are contained in the Serial Peripheral In-
terface section.
A delay-locked loop (DLL) generates internal clock
signals for various stages within the charge pipeline. If
the frequency of the input clock changes, the DLL
may take up to 52µs to regain lock at 250MSPS. The
lock time is inversely proportional to the sample rate.
The DLL has two ranges of operation, slow and fast.
The slow range can be used for sample rates be-
tween 40MSPS and 100MSPS, while the default fast
range can be used from 80MSPS to the maximum
specified sample rate.
Jitter
In a sampled data system, clock jitter directly im-
pacts the achievable SNR performance. The theoreti-
cal relationship between clock jitter (t
shown in Equation 1 and is illustrated in Figure 32.
This relationship shows the SNR that would be
achieved if clock jitter were the only non-ideal fac-
tor. In reality, achievable SNR is limited by internal
factors such as linearity, aperture jitter and thermal
KAD5514P
100
95
90
85
80
75
70
65
60
55
50
1
Figure 32. SNR vs. Clock Jitter
SNR
tj=100ps
Table 1. CLKDIV Pin Settings
CLKDIV Pin
AVDD
AVSS
Float
=
20
10
Equation 1.
Input Frequency - MHz
tj=10ps
log
10
Divide Ratio
tj=1ps
⎛
⎜
⎜
⎝
2
tj=0.1ps
π
2
1
4
f
1
IN
100
t
J
⎞
⎟
⎟
⎠
J
) and SNR is
10 Bits
14 Bits
12 Bits
1000
Preliminary
noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure 1. The internal aper-
ture jitter combines with the input clock jitter in a root-
sum-square fashion, since they are not statistically
correlated, and this determines the total jitter in the
system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference pro-
vides the reference charges used in the successive
approximation operations. The full-scale range of
each A/D is proportional to the reference voltage.
The voltage reference is internally bypassed and is
not accessible to the user.
Digital Outputs
Output data is available as a parallel bus in LVDS-
compatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or
single data rate (SDR) formats. The even numbered
output bits are active in DDR mode. When CLKOUT is
low the MSB and all odd bits are output, while on the
high phase the LSB and all even bits are presented.
Figures 1 and 2 show the timing relationships for
LVDS/CMOS and DDR/SDR modes.
The 48-QFN package option contains six LVDS data
outputs, and therefore can only support DDR mode.
Additionally, the drive current for LVDS mode can be
set to a nominal 3 mA or a power-saving 2 mA. The
lower current setting can be used in designs where
the receiver is in close physical proximity to the ADC.
The applicability of this setting is dependent upon the
PCB layout, therefore the user should experiment to
determine if performance degradation is observed.
The output mode and LVDS drive current are se-
lected via the OUTMODE pin as shown in Table 2.
The output mode can also be controlled through the
SPI port, which overrides the OUTMODE pin setting.
Details on this are contained in the Serial Peripheral
Interface section.
Table 2. OUTMODE Pin Settings
OUTMODE Pin
AVDD
AVSS
Float
LVDS, 3 mA
LVDS, 2 mA
LVCMOS
Mode
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