tda8029hl-c207 NXP Semiconductors, tda8029hl-c207 Datasheet - Page 39

• Manufacturer Part Number: tda8029hl-c207
• Description: Low Power Single Card Reader
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 67:
Table 68:
9397 750 14145
Product data sheet
Bit
7 and 6
5
4
3
2 to 0
Bit
Symbol
Reset
Access
CCR - Clock configuration register (address 1h) bit allocation
CCR - Clock configuration register (address 1h) bit description
8.10.3.6 Power control register (PCR)
Symbol
-
SHL
CST
SC
AC[2:0]
7
-
-
Table 69:
This register is used for starting or stopping card sessions.
6
-
-
AC2
Description
Not used.
Select HIGH Level. This bit determines how the clock is stopped when bit CST = 1. If
SHL = 0, then the clock is stopped at LOW level, if SHL = 1 at HIGH level.
Clock Stop. In case of an asynchronous card, bit CST defines whether the clock to the
card is stopped or not. If CST = 1, then the clock is stopped. If CST = 0, then the clock is
determined by bits AC[2:0] according to
synchronous, ensuring that no spike or unwanted pulse width occurs during changes.
Synchronous Clock. In the event of a synchronous card, then pin CLK is the copy of the
value of bit SC. In reception mode, the data from the card is available to bit UR0 after a
read operation of register URR. In transmission mode, the data is written on the I/O line
of the card when register UTR has been written to.
Asynchronous card clock. When CST = 0, the clock is determined by the state of these
bits according to
f
For switching from
and AC0 must remain the same). For switching from
reverse, only bits CST and SHL must be changed.
When switching from
command and the effective frequency change on pin CLK. The fastest switch is from
1
reverse. The bit CLKSW in register MSR tells the effective switch moment.
In case of f
pin XTAL1.
int
2
0
0
0
0
1
1
1
1
CLK value for an asynchronous card
f
XTAL
is the frequency delivered by the internal oscillator clock circuitry.
to
1
SHL
CLK
2
f
5
0
int
Rev. 03 — 22 February 2005
= f
and reverse, the best regarding duty cycle is from
Table
XTAL
1
n
f
1
, the duty cycle must be ensured by the incoming clock signal on
XTAL
n
69.
f
XTAL
CST
AC1
4
0
0
0
1
1
0
0
1
1
to
read and write
1
to
2
f
1
int
2
f
and reverse, only the bit AC2 must be changed (AC1
int
and reverse, a delay can occur between the
SC
Table
3
0
69. All frequency changes are
AC0
0
1
0
1
0
1
0
1
1
AC2
n
Low power single card reader
2
0
f
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
XTAL
or
1
2
f
int
CLK
f
1
1
1
1
1
1
1
1
XTAL
AC1
2
4
8
2
2
2
2
8
to stopped clock and
f
f
f
f
f
f
f
f
1
0
XTAL
XTAL
XTAL
int
int
int
int
TDA8029
XTAL
to
1
2
f
int
AC0
and
0
0
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