tda8029hl-c207 NXP Semiconductors, tda8029hl-c207 Datasheet - Page 32

• Manufacturer Part Number: tda8029hl-c207
• Description: Low Power Single Card Reader
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 48:
Table 49:
Table 50:
Table 51:
9397 750 14145
Product data sheet
Bit
7 to 0
Bit
7 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
UTR - UART transmit register (address Dh) bit allocation
UTR - UART transmit register (address Dh) bit description
URR - UART receive register (address Dh) bit allocation
URR - UART receive register (address Dh) bit description
8.10.2.1 UART transmit register (UTR)
8.10.2.2 UART receive register (URR)
Symbol
UT[7:0]
Symbol
UR[7:0]
8.10.2 ISO UART registers
UT7
UR7
7
0
7
0
UR6
UT6
6
0
6
0
Description
UART transmit bits. When the microcontroller wants to transmit a character to the card, it
writes the data in direct convention in this register. The transmission:
Description
UART receive bits. When the microcontroller wants to read data from the card, it reads it
from this register in direct convention:
•
•
•
•
•
•
•
•
•
Starts at the end of writing (on the rising edge of signal WR) if the previous character
has been transmitted and if the extra guard time has expired
Starts at the end of the extra guard time if this one has not expired
Does not start if the transmission of the previous character is not completed
With a synchronous card (bit SAN within register UCR2 is set), only UT0 is relevant
and is copied on pin I/O of the card.
With a synchronous card, only UR0 is relevant and is a copy of the state of the
selected card I/O
When needed, this register may be tied to a FIFO whose length ‘n’ is programmable
between 1 and 8; if n > 1, then no interrupt is given until the FIFO is full and the
controller may empty the FIFO when required
With a parity error:
– In protocol T = 0, the received byte is not stored in the FIFO and the error
– In protocol T = 1, the character is loaded in the FIFO and the bit PE is set to the
When the FIFO is full, then bit RBF in the status register USR is set. This bit is reset
when at least one character has been read from URR
When the FIFO is empty, then bit FE is set in the status register USR as long as no
character has been received.
counter is incremented. The error counter is programmable between 1 and 8.
When the programmed number is reached, then bit PE is set in the status
register USR and INT0_N falls LOW. The error counter must be reprogrammed to
the desired value after its count has been reached
programmed value in the parity error counter.
UR5
UT5
5
0
5
0
Rev. 03 — 22 February 2005
UR4
UT4
4
0
4
0
write
read
UR3
UT3
3
0
3
0
UR2
UT2
Low power single card reader
2
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UR1
UT1
1
0
1
0
TDA8029
UR0
UT0
0
0
0
0
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