tda8029hl-c207 NXP Semiconductors, tda8029hl-c207 Datasheet - Page 21

• Manufacturer Part Number: tda8029hl-c207
• Description: Low Power Single Card Reader
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14145
Product data sheet
Fig 7. UART multiprocessor communication, automatic address recognition
UART modes 2 or 3 and SM2 = 1: there is an interrupt if REN = 1, RB8 = 1 and received address is equal to programmed
address.
When own address is received, reset SM2 to receive the data bytes. When all data bytes are received, set SM2 to wait for
the next address.
8.4 Interrupt priority structure
The TDA8029 has a 6-source 4-level interrupt structure.
There are three SFRs associated with the 4-level interrupt: IE, IP and IPH. The Interrupt
Priority High (IPH) register implements the 4-level interrupt structure. The IPH is located
at SFR address B7h.
The function of the IPH is simple and when combined with the IP determines the priority of
each interrupt. The priority of each interrupt is determined as shown in
Table 23:
Table 24:
[1]
[2]
D0
Source
X0
T0
X1
T1
SP
T2
IPH bit n
Level activated.
Transition activated.
0
0
1
1
D1
received address D0 to D7
Priority bits
Interrupt Table
programmed address
D2
IP bit n
SM0
0
1
0
1
1
1
Polling priority
1
2
3
4
5
6
D3
Rev. 03 — 22 February 2005
SM1
Interrupt priority level
level 0 (lowest priority)
level 1
level 2
level 3 (highest priority)
1
0
D4
SM2
COMPARATOR
1
D5
Request bits
IE0
TF0
IE1
TF1
RI, TI
TF2, EXF2
REN
D6
1
TB8
D7
X
Hardware clear
N
Y
N
Y
N
N
RB8
D8
[1]
[1]
Low power single card reader
, Y
, Y
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
[2]
[2]
TI
mdb817
TDA8029
RI
Table
Vector address
(hex)
03
0B
13
1B
23
2B
SCON
(98h)
23.
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