stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 66

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.16 - Address Field Recognition Data Register - AFRDR (1E)H
AF0/15 : ADDRESS FIELD BITS
VIII.17 - Fill Character Register - FCR (20)H
FC0/7 : FILL CHARACTER (eight bits)
VIII.18 - GCI Channels Definition Register 0 - GCIR0 (22)H
The definitions of x and y indices are the same for GCIR0, GCIR1, GCIR2, GCIR3 :
- 0
- y = 0, TDM4 is selected
- y = 1, TDM5 is selected.
VMxy : VALIDATION of MONITOR CHANNELx, MULTIPLEX y :
V*xy
VCxy
ANAxy : ANALOG APPLICATION
66/83
ANA11 VCI11 V*11 VM11 ANA10 VCI10 V*10 VM10 ANA01 VCI01 V*01 VM01 ANA00 VCI00 V*00 VM00
AF15 AF14 AF13 AF12 AF11 AF10
bit15
bit15
bit15
r
x
: VALIDATION of V Starx, MULTIPLEX y
: VALIDATION of Command/Indicate CHANNEL x, MULTIPLEXy
7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5
e
TDM5
AF0/7 ; First byte received; AF8/15: Second byte received.
These two bytes are stored into Address Field Recognition Memory when AFRAR is written by
the microprocessor.
In TransparentMode M1, twomessages are separatedby FILLCHARACTERS andthe detection
of one FILL CHARACTER marks the end of a message.
When this bit is at 1, monitor channel xy is validated.
When this bit is at 0, monitor channel xy is not validated.
On line to reset (if necessary)one MON channel which had been selectedpreviously VMxy must
be put at 0 during 125ms before reselecting this channel. Deselecting one MON channel during
125ms resets this MON channel.
When this bit is at 1, V Star protocol is validated if VMxy=1.
When this bit is at 0, GCI Monitor protocol is validated if VMxy=1.
When this bit is at 1, Command/Indicate channelxy is validated.
When this bit is at 0, Command/Indicate channelxy is not validated.
It is necessary to let VCxy at ”0” during 125ms to initiate the Command/Indicate channel.
When this bit is at 1, Primitive has 6 bits if C/Ixy is validated.
When this bit is at 0, Primitive has 4 bits if C/Ixy is validated.
s
GCI CHANNEL 1
e
r
v
TDM4
AF9
e
After reset (0001)
After reset (0000)
After reset (0000)
bit8
AF8
bit8
bit8
d
AF7
FC7
bit7
bit7
bit7
H
H
H
FC6
AF6
TDM5
FC5
AF5
GCI CHANNEL 0
AF4
FC4
AF3
FC3
AF2
FC2
TDM4
FC1
AF1
bit 0
bit 0
FC0
AF0
bit 0