stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 6

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
LIST OF FIGURES
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PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10 : Structure of the Transmit Circular Queue . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11 : D, C/I and Monitor Channel Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12 : Multi-HDLC connected to P with multiplexed buses . . . . . . . . . . . . . . . .
Figure 13 : Multi-HDLC connected to P with non-multiplexed buses . . . . . . . . . . . .
Figure 14 : Microprocessor Interface for INTEL 80C188 . . . . . . . . . . . . . . . . . . . . . . .
Figure 15 : Microprocessor Interface for INTEL 80C186 . . . . . . . . . . . . . . . . . . . . . . .
Figure 16 : Microprocessor Interface for MOTOROLA 68000 . . . . . . . . . . . . . . . . . . .
Figure 17 : Microprocessor Interface for ST9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18 : 128K x 8 SRAM Circuit Memory Organization . . . . . . . . . . . . . . . . . . . . .
Figure 19 : 512K x 8 SRAM Circuit Memory Organization . . . . . . . . . . . . . . . . . . . . .
Figure 20 : 256K x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21 : 1M x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22 : 4M x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23 : Chain of n Multi-HDLC Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24 : MHDLC Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25 : VCXO Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 26 : The Three Circular Interrupt Memories . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 27 : Clocks received and delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . .
Figure 28 : Synchronization Signals received by the Multi-HDLC . . . . . . . . . . . . . . . .
Figure 29 : GCI Synchro Signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . .
Figure 30 : V* Synchronization Signal delivered by the Multi-HDLC . . . . . . . . . . . . . .
MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 31 : Dynamic Memory Read Signals from the Multi-HDLC . . . . . . . . . . . . . . .
Figure 32 : Dynamic Memory Write Signals from the Multi-HDLC . . . . . . . . . . . . . . .
Figure 33 : Static Memory Read Signals from the Multi-HDLC . . . . . . . . . . . . . . . . . .
Figure 34 : Static Memory Write Signals from the Multi-HDLC . . . . . . . . . . . . . . . . . .
: General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: Switching Matrix Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: Unidirectional and Bidirectional Connections . . . . . . . . . . . . . . . . . . . . . .
: Loop Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: Variable Delay through the matrix with ITDM = 1 . . . . . . . . . . . . . . . . . . .
: Variable Delay through the matrix with ITDM = 0 . . . . . . . . . . . . . . . . . . .
: Constant Delay through the matrix with SI = 1 . . . . . . . . . . . . . . . . . . . . .
: HDLC and DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .
: Structure of the Receive Circular Queue . . . . . . . . . . . . . . . . . . . . . . . . .
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