stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 14

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
II - BLOCK DIAGRAM
The top level functionalities of Multi-HDLC appear on the general block diagram.
Figure 1 : General Block Diagram
There are :
- The switching matrix,
- The time slot assigner,
- The 32 HDLC transmitters with associated DMA
- The 32 HDLC receivers with associated DMA
- The 16 Command/Indicate and Monitor Channel
14/83
VCX OUT
controllers,
controllers,
transmitters belonging to two General Compo-
nent Interfaces(GCI),
VCX IN
XTAL1
XTAL2
P Bus
WDO
DIN6
DIN7
DIN8
26
27
28
7
8
2
3
4
GCI1
GCI0
WATCHDOG
COUNTER
XTAL
INTERFACE
25 24 23 22 21 20
P
32 Rx DMAC
32 Rx HDLC
Recognition
with Adress
Internal Bus
V10
D7
TIME SLOT ASSIGNER FOR MULTIHDLC
16 Rx
C/I
0
1
2
3
4
5
6
7
GCI CHANNEL DEFINITION
Sequence
Analyser
Random
Pseudo
SWITCHING MATRIX
BUS ARBITRATION
16 Rx
MON
n x 64 kb/s
Sequence
Generator
16 Tx
Random
Pseudo
C/I
16 Tx
MON
0
1
2
3
4
5
6
7
39 31
- The 16 Command/Indicate and Monitor Channel
- The memory interface,
- The microprocessor interface,
- The bus arbitration,
- The clock selection and time synchronization
- The interrupt controller,
- The watchdog,
receivers belonging to two General Component
Interfaces (GCI),
function,
32 33 34
for Content. Bus
with CSMA CR
32 Tx DMAC
32 Tx HDLC
35
GCI0
Rx
C/I
36
CONTROLLER
MON
INTERRUPT
GCI1
Rx
37
C/I
Tx
V10
MON
Tx
38 12 10 13
To
Internal
Circuit
INTERFACE
SELECTION
RAM
CLOCK
STLC5464
11
18
17
16 FS
49 INT0
50 INT1
9
5
6
FSCV*
FSCG
DCLK
CB
EC
RAM
Bus