stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 42

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
VI - MEMORY TIMING
VI.1 - Dynamic Memories
Figure 31 : Dynamic Memory Read Signals from the Multi-HDLC
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Symbol
Tw
Th
Tz
Ts
T
a
Delay between Data Strobe from the mP and beginning of cycle
Delay between Masterclock and Edge of each signal delivered by the
MHDLC (30pF)
Delay between NCAS Falling Edge and NCAS rising Edge
Delay between NCAS Rising Edge and end of cycle
Set-up Time Data /NCAS Rising Edge
Hold Time Data/NCAS Rising Edge
NDS fro m P
(or e quivalent)
MASTERCLOCK
a pplied to XTAL1 P in
NRAS 0/3
NCAS 0/1
NWE
ADM0/10
NOE
DM0/15 from
DRAM Circuit
Note : S e e
MBL De finition
HZ
HZ
T
a
Parameter
impe dance outside this time if MBL = 0
Each signal from the MHDLC is high
Tu
a
Tv/2
Total Re ad Cycle
Tv
a
Tw + Tz /2
Ts
Tw
a
Tz
a
Th
Min.
2/f
1/f
1/f
20
a
0
HZ
HZ
Typ.
20
1/f
Max.
2/f
2/f
Unit
ns
ns
ns
ns
ns