stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 57

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

VIII - INTERNAL REGISTERS (continued)
MBL
VIII.3 - Input Multiplex Configuration Register 0 - IMCR0 (04)H
See definition in next Paragraph.
VIII.4 - Input Multiplex Configuration Register 1 - IMCR1 (06)H
ST(i)0 : STEP0 for each Input Multiplex i(0
ST(i)1 : STEP1 for each Input Multiplex i(0
DEL(i); : DELAYED Multiplex i(0
LP (i)
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.5 - Output Multiplex Configuration Register 0 - OMCR0 (08)H
See definition in next Paragraph.
OMV3 DEL3 ST(3)1 ST(3)0 OMV2 DEL2 ST(2)1 ST(2)0 OMV1 DEL1 ST(1)1 ST(1)0 OMV0 DEL0 ST(0)1 ST(0)0
bit15
bit15
bit15
LP3 DEL3 ST(3)1 ST(3)0 LP2 DEL2 ST(2)1 ST(2)0 LP1 DEL1 ST(1)1 ST(1)0 LP0 DEL0 ST(0)1 ST(0)0
LP7 DEL7 ST(7)1 ST(7)0 LP6 DEL6 ST(6)1 ST(6)0 LP5 DEL5 ST(5)1 ST(5)0 LP4 DEL4 ST(4)1 ST(4)0
: Memory Bus Low impedance
: LOOPBACK 0/7
MBL = 1, the shared memory bus is at low impedance between two memory cycles.
The memory bus includes Control bits, Data bits, Address bits. One Multi-HDLC is connected to
the shared memory.
MBL = 0, the shared memory bus is at high impedance between two memory cycles.
Several Muti-HDLCs can be connected to the shared memory. One pull up resistor is
recommended on each wire.
When IMTD = 0 (bit of SMCR), DEL = 1 is not taken into account by the circuit.
LPi = 1, Output Multiplex i is put instead of Input Multiplex i (0 i 7). LOOPBACKis transparent
or not in accordance with OMVi (bit of Output Multiplex Configuration Register).
LPi = 0, Normal case, Input Multiplex i(0
DEL (i) ST (i) 1 ST (i) 2
X
1
1
1
0
0
0
0
0
1
1
0
1
1
0
1
0
1
1
0
1
Each received bit is sampled at 3/4 bit-time without delay.
First bit of the frame is defined by Frame synchronization Signal.
Each received bit is sampled with 1/2 bit-time delay.
Each received bit is sampled with 1 bit-time delay.
Each received bit is sampled with 2 bit-time delay.
Each received bit is sampled with 1/2 bit-time advance.
Each received bit is sampled with 1 bit-time advance
Each received bit is sampled with 2 bit-time advance.
i
7).
After reset (0000)
After reset (0000)
After reset (0000)
bit8
bit8
STEP for each Input Multiplex 0/7 delayed or not
i
i
bit8
7), delayed or not.
7), delayed or not.
i
bit7
bit7
bit7
7) is taken into account.
H
H
H
STLC5464
bit 0
bit 0
bit 0
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