ml2003 Fairchild Semiconductor, ml2003 Datasheet
ml2003
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ml2003 Summary of contents
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... Flat frequency response: ±0.05dB from .3–4 kHz ±0.10dB from .1-20 kHz • Low supply current 4mA max from ±5V supplies • TTL/CMOS compatible digital interface • ML2003 has pin selectable serial or parallel interface; ML2004 serial interface only Block Diagram V P ...
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... ML2003, ML2004 Pin Description Name C3 In serial mode, pin is unused. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. (LATI serial mode, input latch clock which loads the data from the shift register into the latch. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. ...
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... V = 8dBm gain, 1kHz Measure 2nd, IN 3rd harmonic relative to fundamental 8dBm, 1 kHz IN C msg. weighted 4 200mVp-p, 1 kHz sine 2mA OL ML2003, ML2004 Units °C ° Min. Typ. Max. Units -0.05 +0.05 dB -0.05 +0.05 dB -0.05 +0.05 dB -0.05 +0.05 dB -0.1 +0.1 dB -0.05 +0. ...
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... ML2003, ML2004 Electrical Characteristics Unless otherwise specifi MIN Other Bits = 0(0dB Ideal Gain 100pF reference load, digital timing measured at 1 Symbol Parameter Notes V Digital Output High OH Voltage I Input Current, SER/ NS PAR I Input Current, ND All Digital Inputs Except SER/PER ...
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... IPW OPW t PLD Figure 1. Serial Mode Timing Diagram 0 -0.5 ATTEN: V GAIN: V -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 10K 100K 100 /V = .5V ) Figure 3. Amplitude vs Frequency (V IN OUT RMS ML2003, ML2004 RMS = 2V /GAIN SETTING IN RMS GAIN = +24dB GAIN = 0dB GAIN = –24dB 1K 10K FREQUENCY (Hz OUT RMS 100K ) 5 ...
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... ML2003, ML2004 Typical Performance Curves 2.0 1.8 1.6 1.4 GAIN = +24dB 1.2 GAIN = +12dB GAIN = -24dB 1 0.8 0.6 0.4 0 100 FREQUENCY (Hz) Figure 4. Output Noise Voltage vs Frequency 100 ATTEN 8dBm IN GAIN 8dBm/GAIN SETTING IN 1KHz -24 -18 - GAIN SETTING (dB) Figure 6. C S/N vs Gain Setting MSG ...
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... PRODUCT SPECIFICATION Functional Description The ML2003 consists of a coarse gain stage, a fine gain stage, an output buffer, and a serial/parallel digital interface. Gain Stages The analog input goes directly into the op amp input in IN the coarse gain stage. The coarse gain stage has a gain range 22.5dB in 1.5dB steps. The fi ...
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... ML2003, ML2004 Table 2. Coarse Gain Settings (F3- Ideal Gain (dB ATTEN/GAIN = 1 ATTEN/GAIN = - -10 -12 -13 -15 -16 -18 -19.5 ...
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... Figure 11. 9-Bit Latch ML2021 EQUALIZER V OUT µP Figure 13. Typical µP Parallel Interface ML2004 OUT IN OUT V V OUT IN A/D Figure 15. AGC for DSP or Modem Front End ML2003, ML2004 FUNCTION BIT NUMBER ML2003 OUT ATTEN/GAIN C3-C0 F3-F1 8-BIT LATCH ML2004 OUT V IN µP ...
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... ML2003, ML2004 ML2003 OUT ATTEN/GAIN C3-C0 F3-F1 UP/DOWN U/D COMPARATOR 8-BIT COUNTER CLOCK R R1, R2, R3 SETS AGC THRESHOLD Figure 16. Analog AGC V REF CLK1 f CLK1 DETERMINES PEAK ACQUIRE TIME f CLK2 DETERMINES PEAK HOLD TIME Figure 18. Precision Peak Detector (±1%) with Controllable Acquire and Hold Time ...
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... ML2003, ML2004 Ordering Information Part Number ML2003IQ ML2003CP ML2003CQ ML2004IP ML2004CP DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; ...