ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 14

• Manufacturer Part Number: ics1893cy-10
• Description: 3.3-v 10base-t/100base-tx Integrated Phyceiver
• Manufacturer: Integrated Device Technology

Chapter 3 Overview of the ICS1893CY-10
ICS1893CY-10 Rev 1/07
The ICS1893CY-10 is a stream processor. During data transmission, it accepts sequential nibbles from its
MAC (Media Access Control)/Repeater Interface, converts them into a serial bit stream, encodes them, and
transmits them over the medium through an external isolation transformer. When receiving data, the
ICS1893CY-10 converts and decodes a serial bit stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles. It subsequently presents these nibbles to its
MAC/Repeater Interface.
The ICS1893CY-10 implements the OSI model’s physical layer, consisting of the following, as defined by
the ISO/IEC 8802-3 standard:
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The ICS1893CY-10 is transparent to the next layer of the OSI model, the link layer. The link layer has two
sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1893CY-10 can interface
directly to the MAC and offers multiple, configurable modes of operation. Alternately, this configurable
interface can be connected to a repeater, which extends the physical layer of the OSI model.
The ICS1893CY-10 transmits framed packets acquired from its MAC/Repeater Interface and receives
encapsulated packets from another PHY, which it translates and presents to its MAC/Repeater Interface.
Note:
Physical Coding sublayer (PCS)
Physical Medium Attachment sublayer (PMA)
Physical Medium Dependent sublayer (PMD)
Auto-Negotiation sublayer
ICS1893CY-10 Data Sheet - Release
As per the ISO/IEC standard, the ICS1893CY-10 does not affect, nor is it affected by, the
underlying structure of the MAC/repeater frame it is conveying.
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
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Chapter 3 Overview of the ICS1893CY-10