mt4lc4m16r6 Micron Semiconductor Products, mt4lc4m16r6 Datasheet - Page 6

• Manufacturer Part Number: mt4lc4m16r6
• Description: 4 Meg X 16 Edo Dram
• Manufacturer: Micron Semiconductor Products

EDO PAGE MODE (continued)
two methods to disable the outputs and keep them
disabled during the CAS# HIGH time. The first method
is to have OE# HIGH when CAS# transitions HIGH and
keep OE# HIGH for
the DQs, and they will remain disabled (regardless of
the state of OE# after that point) until CAS# falls again.
The second method is to have OE# LOW when CAS#
transitions HIGH and then bring OE# HIGH for a
minimum of
period. This will disable the DQs, and they will remain
disabled (regardless of the state of OE# after that point)
until CAS# falls again (see Figure 3). During other
cycles, the outputs are disabled at
and CAS# are HIGH or at
LOW. The
of RAS# or CAS#, whichever occurs last. WE# can also
perform the function of disabling the output drivers
under certain conditions, as shown in Figure 4.
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the EDO-PAGE-MODE
operation.
DRAM REFRESH
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all rows in the
4 Meg x 16 DRAM array at least once every 64ms (8,192
4 Meg x 16 EDO DRAM
D29_2.p65 – Rev. 5/00
EDO-PAGE-MODE operations are always initiated
The supply voltage must be maintained at the speci-
t
OFF time is referenced from the rising edge
t
OEP anytime during the CAS# HIGH
t
OEHC thereafter. This will disable
t
WHZ after WE# transitions
t
OFF time after RAS#
6
rows for N3 or 4,096 rows for R6). The recommended
procedure is to execute 4,096 CBR REFRESH cycles,
either uniformly spaced or grouped in bursts, every
64ms. The MT4LC4M16N3 internally refreshes two
rows for each CBR cycle, whereas the MT4LC4M16R6
refreshes one row for every CBR cycle. For either device,
executing 4,096 CBR cycles will refresh the entire de-
vice. The CBR REFRESH will invoke the internal refresh
counter for automatic RAS# addressing. Alternatively,
RAS#-ONLY REFRESH capability is inherently provided.
However, with this method, only one row is refreshed
on each cycle. Thus, 8,192 RAS-only REFRESH cycles are
needed every 64ms on the MT4LC4M16N3 in order to
refresh the entire device. JEDEC strongly recommends
the use of CBR REFRESH for this device.
“S” version. The self refresh feature is initiated by
performing a CBR Refresh cycle and holding RAS# low
for the specified
the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended
refresh period of 128ms, or 31.25µs per cycle, when
using a distributed CBR refresh. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
HIGH for a minimum time of
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh, however, if the controller is
using RAS# only or burst CBR refresh then a burst
refresh using
An optional self refresh mode is also available on the
The self refresh mode is terminated by driving RAS#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RC (MIN) is required.
t
RASS. The “S” option allows the user
t
RPS. This delay allows for
4 MEG x 16
EDO DRAM
©2000, Micron Technology, Inc.