mt4lc4m16r6 Micron Semiconductor Products, mt4lc4m16r6 Datasheet - Page 12

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mt4lc4m16r6

Manufacturer Part Number
mt4lc4m16r6
Description
4 Meg X 16 Edo Dram
Manufacturer
Micron Semiconductor Products
Datasheet

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NOTES (continued)
28. Output parameter (DQx) is referenced to
29. Each CASx# must meet minimum pulse width.
30. The last CASx# edge to transition HIGH.
31. Last falling CASx# edge to first rising CASx#
32. Last rising CASx# edge to first falling CASx#
33. Last rising CASx# edge to next cycle’s last rising
34. Last CASx# to go LOW.
4 Meg x 16 EDO DRAM
D29_2.p65 – Rev. 5/00
corresponding CAS# input; DQ0-DQ7 by CASL#
and DQ8-DQ15 by CASH#.
edge.
edge.
CASx# edge.
12
35. V
36. NC pins are assumed to be left floating and are
37. Self refresh and extended refresh for either device
width ≤ 3ns, and the pulse width cannot be
greater than one third of the cycle rate. V
undershoot: V
3ns, and the pulse width cannot be greater than
one third of the cycle rate.
not tested for leakage.
requires that at least 4,096 cycles be completed
every 128ms.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
overshoot: V
IL
(MIN) = -2V for a pulse width ≤
IH
(MAX) = V
CC
4 MEG x 16
EDO DRAM
+ 2V for a pulse
©2000, Micron Technology, Inc.
IL

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