mt4lc4m16r6 Micron Semiconductor Products, mt4lc4m16r6 Datasheet - Page 11

• Manufacturer Part Number: mt4lc4m16r6
• Description: 4 Meg X 16 Edo Dram
• Manufacturer: Micron Semiconductor Products

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10. If CAS# and RAS# = V
11. If CAS# = V
12. Measured with a load equivalent to two TTL
13. If CAS# is LOW at the falling edge of RAS#,
14. The
15. The
4 Meg x 16 EDO DRAM
D29_2.p65 – Rev. 5/00
MHz; T
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured.
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
refresh requirement is exceeded.
measuring timing of input signals. Transition
times are measured between V
between V
specification, all input signals must transit
between V
monotonic manner.
the last valid READ cycle.
gates and 100pF; and V
output data will be maintained from the previous
cycle. To initiate a new cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for
t
only. If
(MAX) limit, then access time was controlled
exclusively by
applied). With or without the
and
t
only. If
(MAX) limit, then access time was controlled
exclusively by
applied). With or without the
t
RCD (MAX) was specified as a reference point
RAD (MAX) was specified as a reference point
AA,
CC
IH
is dependent on output loading and cycle
(MIN) and V
t
t
t
t
RCD (MAX) limit is no longer specified.
CAC must always be met.
RAD (MAX) limit is no longer specified.
RAC, and
A
t
t
RCD was greater than the specified
RAD was greater than the specified
= 25°C.
IL
IH
IL
and V
and V
, data output may contain data from
t
t
CAC (
AA (
t
CAC must always be met.
IL
(MAX) are reference levels for
IH
IL
t
).
RAC and
(or between V
t
IH
RAC [MIN] no longer
, data output is High-Z.
OL
= 0.8V and V
t
T = 2.5ns.
SS
CC
.
t
IH
t
CAC no longer
t
RCD limit,
RAD (MAX) limit,
= +3.3V; f = 1
and V
IL
and V
IL
OH
(or
= 2V.
t
t
IH
t
AA
REF
CP.
t
t
) in a
RCD
RAD
11
16. Either
17.
18.
19. These parameters are referenced to CAS# leading
20. If OE# is tied permanently LOW, LATE WRITE, or
21. A HIDDEN REFRESH may also be performed after
22. RAS#-ONLY REFRESH requires that all 8,192 rows
23. CBR REFRESH for either device requires that at
24. The DQs go High-Z during READ cycles once
25. LATE WRITE and READ-MODIFY-WRITE cycles
26. Column address changed once each cycle.
27. The first CASx# edge to transition LOW.
cycle.
t
achieves the open circuit condition and is not
referenced to V
t
operating parameters.
WRITE cycles. If
an EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle.
MODIFY-WRITE cycles. Meeting these limits
allows for reading and disabling output data and
then applying input data. OE# held HIGH and
WE# taken LOW after CAS# goes LOW results in a
LATE WRITE (OE#-controlled) cycle.
t
WRITE cycle.
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
READ-MODIFY-WRITE operations are not
possible.
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
of the MT4LC4M16N3 or all 4,096 rows of the
MT4LC4M16R6 be refreshed at least once every
64ms.
least 4,096 cycles be completed every 64ms.
or
brought HIGH, the DQs will go High-Z. If OE# is
brought back LOW (CAS# still LOW), the DQs
will provide the previously read data.
must have both
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. If OE# is taken back LOW while CAS#
remains LOW, the DQs will remain open.
OFF (MAX) defines the time at which the output
WCS,
CWD, and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
OFF occur. If CAS# stays LOW while OE# is
t
t
t
RWD,
RWD,
RCH or
t
AWD are not applicable in a LATE
t
t
AWD, and
AWD, and
OH
t
RRH must be satisfied for a READ
t
t
WCS >
OD and
or V
t
OL
WCS applies to EARLY
t
t
.
WCS (MIN), the cycle is
t
CWD define READ-
t
CWD are not restrictive
OEH met (OE# HIGH
4 MEG x 16
EDO DRAM
©2000, Micron Technology, Inc.
t
WCS,
t
RWD,
t
OD