mt48h16m32lfcm-75-it Micron Semiconductor Products, mt48h16m32lfcm-75-it Datasheet - Page 71

• Manufacturer Part Number: mt48h16m32lfcm-75-it
• Description: 512mb 32 Meg X 16, 16 Meg X 32 Mobile Sdram Features
• Manufacturer: Micron Semiconductor Products

Clock Suspend
Figure 51:
PDF: 09005aef82ea3742/Source: 09005aef82ea3752
sdr_mobile_sdram_cmd_op_timing_dia_fr4.08__4.fm - Rev. B 4/08 EN
Clock Suspend During WRITE Burst
Notes:
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended (see
examples in Figure 51 and Figure 52 on page 72).
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
1. For this example, BL = 4 or greater, and DQM is LOW.
Command
Internal
Address
clock
CKE
CLK
D
IN
NOP
T0
WRITE
Bank,
Col n
D
T1
n
IN
71
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
n + 1
T4
D
IN
Don’t Care
T5
NOP
n + 2
D
IN
©2007 Micron Technology, Inc. All rights reserved.
SDR Mobile SDRAM
Operations