mt48h16m32lfcm-75-it Micron Semiconductor Products, mt48h16m32lfcm-75-it Datasheet - Page 69

• Manufacturer Part Number: mt48h16m32lfcm-75-it
• Description: 512mb 32 Meg X 16, 16 Meg X 32 Mobile Sdram Features
• Manufacturer: Micron Semiconductor Products

Figure 49:
Power-Down
PDF: 09005aef82ea3742/Source: 09005aef82ea3752
sdr_mobile_sdram_cmd_op_timing_dia_fr4.08__4.fm - Rev. B 4/08 EN
Command
BA0, BA1
Address
DQM
CKE
A10
CLK
DQ
High-Z
Precharge all
t CKS
active banks
t CMS
Self Refresh Mode
t
AS
PRECHARGE
Single bank
All banks
Bank(s)
T0
Notes:
t CKH
t CMH
t
AH
t CK
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock ball) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued
according to the distributed refresh rate (
REFRESH and AUTO REFRESH utilize the row refresh counter.
1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
t RP
required.
T1
NOP
t CH
Enter self refresh mode
t CKS
t CL
REFRESH
AUTO
CLK stable prior to exiting
T2
self refresh mode
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(Restart refresh time base)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Exit self refresh mode
t
REF/refresh row count) as both SELF
Tn + 1
t XSR
NOP
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To + 1
t
XSR because time is
©2007 Micron Technology, Inc. All rights reserved.
SDR Mobile SDRAM
To + 2
REFRESH
AUTO
Don’t Care
Operations