mma1605nwr2 Freescale Semiconductor, Inc, mma1605nwr2 Datasheet - Page 41

• Manufacturer Part Number: mma1605nwr2
• Description: Dsi Inertial Sensor
• Manufacturer: Freescale Semiconductor, Inc

4.2.1.14
when it is sent to the DSI Global Address of ‘0000’.
eration output value of ΔDFLCT_xxx within t
command is received.
self test circuitry remains disabled, and the ST bit is cleared in the response. Self-test locking is described in
Table 55. Enable Self-Test Command Bit Definitions
Table 58. Enable Self Test Response Bit Definitions
Sensors
Freescale Semiconductor
Table 54. Enable Self-Test Command
Table 57. Long Response - Enable Self-Test Command
D[15]
D[7]
A[3]
The Enable Self Test command is supported in the following command formats:
The data bits D[7:0] in the command are only used in the CRC calculation. The device ignores the Enable Self Test command
The Enable Self Test Command applies a voltage to the self test plate of the transducer which results in a delta in the accel-
Activation of the self test circuit is inhibited if the self-test locking has been activated. If self-test locking is activated, the internal
⎯
Table 56. Short Response - Enable Self-Test Command
Bit Field
Bit Field
D[14]
AT[1:0]
C[3:0]
A[3:0]
D[7:0]
A[3:0]
0
NV
ST
S
U
D[14]
D[6]
A[2]
⎯
D[13]
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference
• Enhanced Short Command as configured by the Format Control Command (Reference
0
Enable Self-Test Command
D[13]
D[5]
A[1]
⎯
Enable Self-Test Command = ‘1101’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference
Attribute bits located in Register DEVCFG1 (Reference
This bit indicates whether internal self-test circuitry is active
1 - Self-test active
0 - Self-test disabled
This bit is set if the voltage at HCAP is below the threshold specified in
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
DSI device address. This field contains the device address.
D[12]
0
D[12]
D[4]
A[0]
⎯
D[11]
Data
Table 59
0
D[11]
D[3]
⎯
0
D[10]
for conditions that set the S bit.
0
D[10]
D[2]
⎯
0
D[9]
ST_ACT_xxx
0
D[1]
D[9]
⎯
0
D[8]
0
D[0]
D[8]
Response
, as specified in
⎯
0
Data
D[7]
NV
A[3]
D[7]
A[3]
NV
Section
D[6]
U
Definition
A[2]
D[6]
A[2]
Definition
U
3.1.4.2)
Address
Section
D[5]
ST
Section
A[1]
D[5]
A[1]
ST
2. This remains present until the Disable Self Test
D[4]
0
2. Refer to
A[0]
D[4]
A[0]
0
AT[1]
D[3]
AT[1]
C[3]
D[3]
Section 3.3.2
1
AT[0]
D[2]
AT[0]
C[2]
D[2]
Command
1
D[1]
for details.
S
Section
Section
C[1]
D[1]
S
0
D[0]
Section
0
4.2.1.11)
C[0]
D[0]
4.2.1.11)
1
0
MMA16xxNW
CRC
4 bits
4.2.1.13.
CRC
CRC
4 bits
4 bits
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