mma1605nwr2 Freescale Semiconductor, Inc, mma1605nwr2 Datasheet - Page 31

• Manufacturer Part Number: mma1605nwr2
• Description: Dsi Inertial Sensor
• Manufacturer: Freescale Semiconductor, Inc

4.2.1.2
The data bits D[7:0] in the command are only used in the CRC calculation.
Table 17. Request Status Command Bit Definitions
Table 19. Long Response - Request Status Command
Table 16. Request Status Command
D[15]
Sensors
Freescale Semiconductor
D[7]
A[3]
The Request Status command is supported in the following command formats:
The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
Table 20. Request Status Response Bit Definitions
⎯
Table 18. Short Response - Request Status Command
Bit Field
Bit Field
D[14]
AT[1:0]
C[3:0]
A[3:0]
D[7:0]
A[3:0]
0
NV
ST
D[14]
U
S
D[6]
A[2]
⎯
D[13]
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference
• Enhanced Short Command as configured by the Format Control Command (Reference
Request Status Command
0
D[13]
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference
Attribute bits located in Register DEVCFG1 (Reference
This bit indicates whether internal self-test circuitry is active
1 - Self-test active
0 - Self-test disabled
This bit is set if the voltage at HCAP is below the threshold specified in
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
DSI device address. This field contains the device address.
Shaded bits are transmitted to meet the response message length of the received message
D[5]
A[1]
⎯
Request Status Command = ‘0001’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
D[12]
0
D[12]
A[0]
D[4]
⎯
Table 59
D[11]
Data
0
D[11]
D[3]
⎯
0
for conditions that set the S bit.
D[10]
0
D[10]
D[2]
0
⎯
D[9]
0
D[9]
D[1]
⎯
0
D[8]
0
D[8]
D[0]
Response
0
⎯
Data
D[7]
NV
D[7]
Section
A[3]
NV
A[3]
D[6]
U
Definition
3.1.4.2)
D[6]
A[2]
A[2]
Definition
U
Address
D[5]
ST
Section
D[5]
A[1]
A[1]
ST
2. Refer to
D[4]
0
D[4]
A[0]
A[0]
0
AT[1]
D[3]
Section 3.3.2
AT[1]
D[3]
C[3]
0
AT[0]
D[2]
AT[0]
D[2]
C[2]
Command
for details.
0
D[1]
S
Section 4.2.1.11
Section 4.2.1.11
D[1]
C[1]
S
0
D[0]
0
D[0]
C[0]
0
1
0 to 8 bits
MMA16xxNW
)
)
CRC
0 to 8 bits
0 to 8 bits
CRC
CRC
31