mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 38

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

Analog comparator interrupt is generated by ACF in ACCON. It will not be cleared by hardware when the service
routine is vectored to.
PWM-Timer interrupt is generated by CF in CCON. It will not be cleared by hardware when the service routine is
vectored to.
All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had
been set or cleared by hardware. In other words, interrupts can be generated or pending interrupts can be
canceled in software.
How hardware see the interrupts
Each interrupt flag is sampled at every system clock cycle. The samples are polled during the next system clock.
If one of the flags was in a set condition at first cycle, the second cycle(polling cycle) will find it and the interrupt
system will generate an hardware LCALL to the appropriate service routine as long as it is not blocked by any of
the following conditions.
Block conditions:
Any of these three conditions will block the generation of the hardware LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine.
Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one or more
instruction will be executed before any interrupt is vectored to.
The polling cycle is repeated with each clock cycle. Note that if an interrupt flag is active but not being responded
to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied
interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not being
responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed,
the denied interrupt will not be serviced. The interrupt flag was once active but not serviced is not kept in memory.
Each polling cycle is new.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
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An interrupt of equal or higher priority level is already in progress.
The current cycle (polling cycle) is not the final cycle in the execution of the instruction in progress.
The instruction in progress is RETI or any write to the IE, IP or IPH registers.
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