mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 2

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

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10. Configurable I/O Ports................................................................................ 25
11. Interrupt...................................................................................................... 32
12. Timers/Counters......................................................................................... 39
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© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
General Description ..................................................................................... 5
Features ....................................................................................................... 6
Block Diagram.............................................................................................. 8
Special Function Register ............................................................................ 9
4.1. SFR Map............................................................................................................................... 9
4.2. SFR Bit Assignment............................................................................................................ 10
4.3. SFR Paging......................................................................................................................... 11
Pin Configurations...................................................................................... 12
5.1. Package Instruction ............................................................................................................ 12
MG82FE(L)308AD48 .................................................................................................................. 12
5.2. Pin Description.................................................................................................................... 14
System Clock ............................................................................................. 15
6.1. Clock Structure ................................................................................................................... 15
6.2. Clock Register..................................................................................................................... 15
8051 CPU Function Description................................................................. 18
7.1. CPU Register ...................................................................................................................... 18
7.2. CPU Timing......................................................................................................................... 19
7.3. CPU Addressing Mode ....................................................................................................... 19
Memory Organization................................................................................. 20
8.1. On-Chip Program Flash ...................................................................................................... 20
8.2. On-Chip Data RAM ............................................................................................................. 21
8.3. On-chip expanded RAM (XRAM)........................................................................................ 22
8.4. Declaration Identifiers in a C51-Compiler ........................................................................... 23
Dual Data Pointer Register (DPTR) ........................................................... 24
10.1. IO Structure......................................................................................................................... 25
10.2. I/O Port Register ................................................................................................................. 27
11.1. Interrupt Structure ............................................................................................................... 32
11.2. Interrupt Register ................................................................................................................ 33
12.1. Timer0 and Timer1.............................................................................................................. 39
10.1.1. Quasi-Bidirectional IO Structure ................................................................................... 25
10.1.2. Push-Pull Output Structure........................................................................................... 26
10.1.3. Input-Only (High Impedance Input) Structure............................................................... 26
10.1.4. Open-Drain Output Structure ....................................................................................... 27
10.2.1. Port 0 Register ............................................................................................................. 28
10.2.2. Port 1 Register ............................................................................................................. 28
10.2.3. Port 2 Register ............................................................................................................. 29
10.2.4. Port 3 Register ............................................................................................................. 29
10.2.5. Port 4 Register ............................................................................................................. 30
10.2.6. Port 5 Register ............................................................................................................. 30
10.2.7. Port 6 Register ............................................................................................................. 31
10.2.8. Port 7 Register ............................................................................................................. 31
12.1.1. Mode 0 Structure .......................................................................................................... 39
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