EMD12164P Emlsi Inc., EMD12164P Datasheet - Page 3

• Manufacturer Part Number: EMD12164P
• Description: 512m 32m X 16 Mobile Ddr Sdram
• Manufacturer: Emlsi Inc.

Table 2: Pad Description
CK, CKB
CKE
CSB
RASB, CASB,
WEB
DQM0, DQM1
BA0, BA1
A0 - A12
DQ0-DQ15
DQS0, DQS1
VDD
VSS
VDDQ
VSSQ
Symbol
Supply Power Supply
Supply Ground
Supply I/O Power Supply
Supply I/O Ground
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
Clock : CK and CKB are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK and negative edge of CKB. Input and output data is referenced
to the crossing of CK and CKB(both directions of crossing). Internal clock signals are derived from CK/
CKB.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operation(all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is
synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously.
Input buffers, excluding CK, CKB and CKE, are disabled during power-down and self refresh mode
which are contrived for low standby power consumption.
Chip Select : CSB enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when CSB is registered HIGH. CSB provides for external bank selection on
systems with multiple banks. CSB is considered part of the command code.
Command Inputs: CASB, RASB, and WEB(along with CSB) define the command being entered.
Input Data Mask : DQM is an input mask signal for write data. Input data is masked when DQM is sam-
pled HIGH along with that input data during a WRITE access. DQM is sampled on both edges of DQS.
Although DQM pins are input-only, the DQM loading matches the DQ and DQS loading. For x16
devices, DQM0 corresponds to the data on DQ0-DQ7, DQM1 corresponds to the data on DQ8-DQ15.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
Address Inputs: provide the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ / WRITE commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the op-code during a MODE REGISTER SET com-
mand.
Data Bus: Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered with
write data. Used to capture write data. For x16 device, DQS0 corresponds to the data on DQ0-DQ7,
DQS1 corresponds to the data on DQ8-DQ15.
3
Descriptions
512M: 32M x 16 Mobile DDR SDRAM
EMD12164P
Preliminary
Rev 0.0