ds3104 Maxim Integrated Products, Inc., ds3104 Datasheet - Page 81

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ds3104

Manufacturer Part Number
ds3104
Description
Ds3104 Line Card Timing Ic With Synchronous Ethernet Support
Manufacturer
Maxim Integrated Products, Inc.
Datasheet

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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Automatic Bandwidth Selection (AUTOBW). See Section 7.7.3.
Bit 3: Limit Integral Path (LIMINT). When this bit is set to 1, the T0 DPLL’s integral path is limited (i.e., frozen)
when the DPLL reaches minimum or maximum frequency, as set by the HARDLIM field in
When the integral path is frozen, the current DPLL frequency in registers FREQ1, FREQ2, and
frozen. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in. See Section 7.7.3.
Rev: 012108
________________________________________________________________________________________ DS3104-SE
0 = Always selects locked bandwidth from the
1 = Automatically selects either locked bandwidth
0 = Do not freeze integral path at min/max frequency.
1 = Freeze integral path at min/max frequency.
register) as appropriate.
AUTOBW
7
1
6
1
MCR9
Master Configuration Register 9
3Bh
5
1
T0LBW
4
1
(T0LBW
register.
LIMINT
register) or acquisition bandwidth
3
1
2
0
DLIMIT1
1
1
FREQ3
(T0ABW
and DLIMIT2.
81 of 136
0
1
is also

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