ds3104 Maxim Integrated Products, Inc., ds3104 Datasheet - Page 17

• Manufacturer Part Number: ds3104
• Description: Ds3104 Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

7.
7.1
The DS3104-SE has eight input clocks pins and three frame-sync input pins. The device can output as many as
nine different clock frequencies on 16 output clock pins. There are two separate DPLLs in the device: the high-
performance T0 DPLL and the simpler the T4 DPLL. Both DPLLs can generate output clocks. See
Four of the input clock pins are single-ended and can accept clock signals from 2kHz to 125MHz. The other four
are differential inputs that can accept clock signals up to 156.25MHz. The differential inputs can be configured to
accept differential LVDS or LVPECL signals or single-ended CMOS/TTL signals.
Each input clock can be monitored continually for activity, and each can be marked unavailable or given a priority
number. Separate input priority numbers are maintained for the T0 DPLL and the T4 DPLL. Except in special
modes, the highest priority valid input is automatically selected as the reference for each path. SRFAIL is set or
cleared based on activity and/or frequency of the selected input.
Both the T0 DPLL and the T4 DPLL can directly lock to many common telecom and datacom frequencies,
including, but not limited to, 8kHz, DS1, E1, 10MHz, 19.44MHz, and 38.88MHz as well as Ethernet frequencies
including 25MHz, 62.5MHz, 125MHz, and 156.25MHz. The DPLLs can also lock to multiples of the standard direct-
lock frequencies including 8kHz.
The T0 DPLL is the high-performance path with all the features needed for synchronizing a line card to dual
redundant system timing cards. The T4 DPLL is a simpler auxiliary path typically used to provide a clock derived
from an incoming line rate to system timing cards. The T4 APLL can be connected to either the T4 DPLL or the T0
DPLL to provide more low-jitter output frequencies from the T0 DPLL. There is also a dedicated low-jitter APLL
output that operates at 312.5MHz for 10G Ethernet applications.
Using the optional PLL bypass, the T4 selected reference, after any frequency division, can be directly output on
any of the OC1 to OC7 output clock pins.
Both DPLLs have these features:
The T0 DPLL has these additional features not available in the T4 DPLL:
The T4 DPLL has these additional features not available in the T0 DPLL:
Rev: 012108
________________________________________________________________________________________ DS3104-SE
Functional Description
Overview
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Automatic reference selection based on input activity and priority
Optional manual reference selection/forcing
Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor
Ability to lock to several common telecom and Ethernet frequencies plus multiples of any standard
direct lock frequency
Frequency conversion between input and output using digital frequency synthesis
Combined performance of a stable, consistent digital PLL and low-jitter analog output PLLs
A full state machine for automatic transitions among free-run, locked, and holdover states
Nonrevertive reference switching mode
Phase build-out for reference switching (“hitless”)
Output vs. input phase offset control
13 bandwidth selections from 0.1Hz to 400Hz (vs. six selections for the T4 DPLL)
Noise rejection circuitry for low-frequency references
Output phase alignment to input frame-sync signal
Instant digital one-second averaging and free-run holdover modes
Three bandwidth selections limited to 18Hz to 70Hz
Optional mode to measure the phase difference between two input clocks
Figure
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