ds3104 Maxim Integrated Products, Inc., ds3104 Datasheet - Page 23

• Manufacturer Part Number: ds3104
• Description: Ds3104 Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

The reference selection algorithm for each DPLL chooses the highest priority valid input clock to be the selected
reference. To select the proper input clock based on these criteria, the selection algorithm maintains a priority table
of valid inputs. The top three entries in this table and the selected reference are displayed in the
PTAB2
for the T0 DPLL. When T4T0 = 1, they indicate the highest priority input clocks for the T4 DPLL.
If two or more input clocks are given the same priority number, those inputs are prioritized among themselves using
a fixed circular list. If one equal-priority clock is the selected reference but becomes invalid, the next equal-priority
clock in the list becomes the selected reference. If an equal-priority clock that is not the selected reference
becomes invalid, it is simply skipped over in the circular list. The selection among equal-priority inputs is inherently
nonrevertive, and revertive switching mode (see next paragraph) has no effect in the case where multiple equal-
priority inputs have the highest priority.
An important input to the selection algorithm for the T0 DPLL is the REVERT bit in the
mode (REVERT = 1), if an input clock with a higher priority than the selected reference becomes valid, the higher
priority reference immediately becomes the selected reference. In nonrevertive mode (REVERT = 0), the higher
priority reference does not immediately become the selected reference but does become the highest priority
reference in the priority table (REF1 field in the
highest priority valid input when the selected reference goes invalid, regardless of the state of the REVERT bit.) For
many applications, nonrevertive mode is preferred for the T0 DPLL because it minimizes disturbances on the
output clocks due to reference switching. The T4 DPLL always operates in revertive mode.
In nonrevertive mode, planned switchover to a newly valid higher priority input clock can be done manually under
software control. The validation of the new higher priority clock sets the corresponding status bit in the
MSR2
respond to this change of state by briefly enabling revertive mode (toggling REVERT high then back low) to drive
the switchover to the higher priority clock.
7.6.3 Forced Selection
The T0FORCE field in the
specified input clock to be the selected reference for the T0 and T4 DPLLs, respectively. In both T0FORCE and
T4FORCE, values of 0 and 15 specify normal operation with automatic reference selection. Values from 1 to 6 and
8 and 9 specify the input clock to be the forced selection; other values will cause no input to be selected. Internally,
forcing is accomplished by giving the specified clock the highest priority (as specified in PTAB1:REF1). In revertive
mode (MCR3:REVERT = 1) the forced clock automatically becomes the selected reference (as specified in
PTAB1:SELREF) as well. In nonrevertive mode (T0 DPLL only) the forced clock only becomes the selected
reference when the existing selected reference is invalidated or made unavailable for selection. In both revertive
and nonrevertive modes when an input is forced to be the highest priority, the normal highest priority input (when
no input is forced) is listed as the second-highest priority (PTAB2:REF2) and the normal second-highest priority
input is listed as the third-highest priority (PTAB2:REF3).
When the T4 DPLL is used to measure the phase difference between the T0 DPLL selected reference and another
reference input by setting the T0CR1:T4MT0 bit, the T4FORCE field in the
other reference input.
7.6.4 Ultra-Fast Reference Switching
By default, disqualification of the selected reference and switchover to another reference occurs when the activity
monitor’s inactivity alarm threshold has been crossed, a process that takes on the order of hundreds of
milliseconds or seconds. For the T0 DPLL, an option for extremely fast disqualification and switchover is also
available. When ultra-fast switching is enabled (MCR10:UFSW = 1), if the fast activity monitor detects
approximately two missing clock cycles, it declares the reference failed by forcing the leaky bucket accumulator to
its upper threshold (see Section 7.5.2) and initiates reference switching. This is in addition to setting the SRFAIL bit
in
occurs, the T0 DPLL transitions to the prelocked 2 state, which allows switching to occur faster by bypassing the
loss-of-lock state. The device should be in nonrevertive mode when ultra-fast switching is enabled. If the device is
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MSR2
register, which can drive an interrupt request on the INTREQ pin if needed. System software can then
registers. When T4T0 = 0 in the
and optionally generating an interrupt request, as described in Section 7.5.3. When ultra-fast switching
MCR2
register and the T4FORCE field in the
MCR11
PTAB1
register, these registers indicate the highest priority input clocks
register). (The selection algorithm always switches to the
MCR4
MCR4
register provide a way to force a
register can be used to select the
MCR3
register. In revertive
PTAB1
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MSR1
and
or