ds3104 Maxim Integrated Products, Inc., ds3104 Datasheet - Page 64
ds3104
Manufacturer Part Number
ds3104
Description
Ds3104 Line Card Timing Ic With Synchronous Ethernet Support
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3104.pdf
(136 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 and 5 to 0: Input Clock Valid Status (IC8 and IC[6:1]). Each of these real-time status bits is set to 1 when
the corresponding input clock is valid. An input is valid if it has no active alarms (ACT = 0, LOCK = 0 in the
corresponding
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Holdover Frequency Ready (HORDY). This real-time status bit is set to 1 when the T0 DPLL has a
holdover value that has been averaged over the one-second holdover averaging period. See the related latched
status bit in
Bit 0: Input Clock Valid Status (IC9). This bit has the same behavior as the bits in
Rev: 012108
________________________________________________________________________________________ DS3104-SE
0 = Invalid
1 = Valid
MSR4
ISR
IC8
—
7
0
7
0
and Section 7.7.1.6.
register). See also the
HORDY
—
6
0
6
0
VALSR1
Input Clock Valid Status Register 1
0Eh
VALSR2
Input Clock Valid Status Register 2
0Fh
MSR1
IC6
—
5
0
5
0
register and Section 7.5.
IC5
—
4
0
4
0
IC4
—
3
0
3
0
IC3
—
2
0
2
0
VALSR1
but for the IC9 clock.
IC2
—
1
0
1
0
64 of 136
IC1
IC9
0
0
0
0
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