isl6333 Intersil Corporation, isl6333 Datasheet - Page 32

• Manufacturer Part Number: isl6333
• Description: Three-phase Buck Pwm Controller With Integrated Mosfet Drivers And Light Load Efficiency Enhancements For Intel Vr11.1 Applications
• Manufacturer: Intersil Corporation

and the end of the lower-MOSFET conduction interval
respectively.
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P
UPPER MOSFET POWER CALCULATION
In addition to r
upper-MOSFET losses are due to currents conducted across
the input voltage (V
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times,
the lower-MOSFET body-diode reverse-recovery charge, Q
and the upper MOSFET r
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
the required time for this commutation is t
approximated associated power loss is P
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET
reverse-recovery charge, Q
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P
Finally, the resistive part of the upper MOSFET is given in
Equation 29 as P
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 26, 27, 28 and 29. Since the power
P
P
P
P
P
LOW 2 ( )
UP 1 ( )
UP 2 ( )
UP 3 ( )
UP 4 ( )
≈
≈
≈
=
V
V
r
=
DS ON
V
IN
IN
V
IN
D ON
(
⋅
⋅
(
⎛
⎝
DS(ON)
⎛
⎜
⎝
⋅
I
----- -
I
----- -
Q
N
N
M
M
)
rr
⋅
)
UP(4).
+
–
d
⋅
⋅
IN
I
--------- -
I
--------- -
f
f
P-P
P-P
⋅
S
2
2
S
) during switching. Since a substantially
⎛
⎜
⎝
⋅
losses, a large portion of the
⎞
⎟
⎠
I
----- -
⎞
⎠
N
.
⎛
⎜
⎝
M
I
------
⋅
⋅
N
M
⎞
⎟
⎠
DS(ON)
⎛
⎜
⎝
⎛
⎜
⎝
2
t
----
+
t
----
2
2
2
1
+
rr
I P-P
-----------
⎞
⎟
⎠
⎞
⎟
⎠
UP(2).
. Since the inductor current has
32
I
--------- -
2
2
⋅
P-P
12
⋅
. In Equation 27, the
f
f
S
⎞
⎟
⎠
S
2
UP(3)
conduction loss.
⋅
t d1
.
ISL6333, ISL6333A, ISL6333B, ISL6333C
+
shown in Equation 28.
⎛
⎜
⎜
⎝
LOW(1)
I
------
N
M
UP(1).
1
–
and the
I
-----------
P-P
2
and P
.
⎞
⎟
⎟
⎠
rr
⋅
, it is
t
d2
(EQ. 25)
LOW(2)
(EQ. 26)
(EQ. 27)
(EQ. 28)
(EQ. 29)
rr
,
.
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controllers. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See “Layout Considerations” on
page 38 for thermal transfer improvement suggestions.
When designing the controllers into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 30 and 31, respectively.
In Equations 30 and 31, P
power loss and P
loss; the gate charge (Q
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
N
respectively; N
I
without capacitive load and is typically 75mW at 300kHz.
P
Q
P
P
I
Q2
DR
Qg_TOT
*VCC product is the quiescent power of the controller
Qg_Q2
Qg_Q1
are the number of upper and lower MOSFETs per phase,
=
⎛
⎝
3
-- - Q
2
=
=
=
⋅
Q
3
-- - Q
2
P
G1
G2
⋅
Qg_Q1
PHASE
⋅
G1
⋅
N
Qg_Q2
PVCC F
Q1
⋅
+
PVCC F
+
P
is the number of active phases. The
Q
Qg_Q2
G1
⋅
is the total lower gate drive power
G2
Qg_Q1
SW
⋅
and Q
⋅
N
SW
⋅
+
Q2
N
I
Q
Q2
⋅
is the total upper gate drive
⎞ N
⎠
G2
N
⋅
⋅
VCC
Q1
⋅
) is defined at the
N
Q
PHASE
PHASE
⋅
is the driver total
N
PHASE
⋅
F
Qg_TOT
SW
+
April 10, 2008
I
Q
(EQ. 31)
, due to
(EQ. 30)
Q1
FN6520.0
and