isl6333 Intersil Corporation, isl6333 Datasheet - Page 28

• Manufacturer Part Number: isl6333
• Description: Three-phase Buck Pwm Controller With Integrated Mosfet Drivers And Light Load Efficiency Enhancements For Intel Vr11.1 Applications
• Manufacturer: Intersil Corporation

regulate BYP1 to around 11.2V at a 50mA average load
current. In the low power state, when PSI# is low, BYP1 is
regulated down to one of two voltages depending on the
state of the SS pin. If the SS pin is tied to ground through the
R
average load current. If the SS pin is tied to VCC through the
R
average load current.
It is possible to disable the internal GVOT regulator by
shorting the PVCC1 pin to the BYP1 pin. This essentially
bypasses the internal regulator setting the Channel 1 lower
gate drive voltage, LVCC1, to the voltage input on the
PVCC1 pin.
Upper MOSFET Gate Drive Voltage Versatility
The controllers provide the user flexibility in choosing the
upper MOSFET gate drive voltage for efficiency
optimization. The controllers tie all the upper gate drive rails
together to the PUVCC pin. Simply applying a voltage from
+5V up to +12V on PUVCC sets all of the upper gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC1, PVCC2_3, PUVCC, BYP1 and VID pins. When
the conditions are met, the controllers begin soft-start. Once
the output voltage is within the proper window of operation,
the controllers assert VR_RDY.
Enable and Disable
While in shutdown mode, the LGATE and UGATE signals
are held low to assure the MOSFETs remain off. The
following input conditions must be met before the controllers
SS
SS
FIGURE 15. POWER SEQUENCING USING
resistor, BYP1 is regulated down to 5.75V at a 50mA
resistor, BYP1 is regulated down to 7.75V at a 50mA
THRESHOLD-SENSITIVE ENABLE (EN)
FUNCTION
FAULT LOGIC
CIRCUIT
SOFT-START
POR
ISL6333 INTERNAL CIRCUIT
AND
28
ISL6333, ISL6333A, ISL6333B, ISL6333C
ENABLE
COMPARATOR
+
-
0.86V
VCC
EN
PVCC1
PVCC2_3
PUVCC
BYP1
are released from shutdown mode to begin the soft-start
startup sequence:
Once all of these conditions are met the controllers will begin
the soft-start sequence and will ramp the output voltage up
as described in “Soft-Start” on page 28.
Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence if composed of four
periods, as shown in Figure 16. Once the controllers are
released from shutdown and soft-start begins (as described
in “Enable and Disable” on page 28), there will be a fixed
delay period, t
the controllers will begin the first soft-start ramp, increasing
the output voltage until it reaches the 1.1V VBOOT voltage.
The controllers will then regulate the output voltage at 1.1V
for another fixed delay period, t
end of the t
signals. It is recommended that the VID codes be set no
later then 50µs into period t
controllers will initiate the second soft-start ramp, regulating
the output voltage up to the VID voltage ± any offset or droop
voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 19.
t
1. The bias voltage applied at VCC must reach the internal
2. The voltage on EN must be above 0.86V. The enable
3. The driver bias voltage applied at the PVCC1, PVCC2_3,
SS
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the controllers are guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the controllers will not inadvertently turn off unless the
bias voltage drops substantially (see “Electrical
Specifications” on page 13).
comparator holds the controllers in shutdown until the
voltage at EN rises above 0.86V. The enable comparator
has 104mV of hysteresis to prevent bounce.
PVCC2, PVCC3, PUVCC, and BYP1 pins must reach the
internal power-on reset (POR) rising threshold.
Hysteresis between the rising and falling thresholds
assure that once enabled, the controllers will not
inadvertently turn off unless the bias voltages drops
substantially (see “Electrical Specifications” on page 13).
=
t
d1
+
d3
t
d2
d1
period, the controllers will read the VID
+
, of typically 1.10ms. After this delay period,
t
d3
+
t
d4
d3
. If the VID code is valid, the
d3
, of typically 93µs. At the
April 10, 2008
(EQ. 19)
FN6520.0