isl6333 Intersil Corporation, isl6333 Datasheet - Page 29

• Manufacturer Part Number: isl6333
• Description: Three-phase Buck Pwm Controller With Integrated Mosfet Drivers And Light Load Efficiency Enhancements For Intel Vr11.1 Applications
• Manufacturer: Intersil Corporation

During t
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator, which
is defined by the resistor R
ramp times, t
Equations 20 and 21:
For example, when VID is set to 1.5V and the R
100kΩ, the first soft-start ramp time t
second soft-start ramp time t
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t
typical value for t
Pre-Biased Soft-Start
The controllers also have the ability to start up into a
pre-charged output, without causing any unnecessary
t
t
d2
d4
GND>
GND>
FIGURE 17. SOFT-START WAVEFORMS FOR ISL6333-BASED
=
=
1.1 R
V
d2
OUTPUT PRECHARGED
VID
BELOW DAC LEVEL
⋅
and t
FIGURE 16. SOFT-START WAVEFORMS
–
SS
OUTPUT PRECHARGED
d2
1.1
MULTI-PHASE CONVERTER
ABOVE DAC LEVEL
⋅
V
d4
and t
8 10
OUT
d5
⋅
t1
t
⋅
, the controllers digitally control the DAC
d1
R
VR_RDY
SS
is 93µs.
t2
, 500mV/DIV
EN
d4
–
3
⋅
(
, can be calculated based on
8 10
μs
⋅
t
)
d2
SS
d4
500µs/DIV
–
29
3
on the SS pin. The soft-start
will be 320µs.
(
μs
t
d3
)
t3
ISL6333, ISL6333A, ISL6333B, ISL6333C
d2
t
d4
will be 880µs and the
t
V
d5
OUT
EN (5V/DIV)
SS
d5
(0.5V/DIV)
. The
is set at
(EQ. 20)
(EQ. 21)
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by
the DAC setting. Should the output be pre-charged to a level
exceeding the DAC setting, the output drives are enabled at
the end of the soft-start period, leading to an abrupt correction
in the output voltage down to the DAC-set level.
Fault Monitoring and Protection
The controllers actively monitor the output voltage and
current to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to a microprocessor
load. One common VR_RDY indicator is provided for linking
to external system monitors. The schematic in Figure 18
outlines the interaction between the fault monitors and the
VR_RDY signal..
VR_RDY Signal
The VR_RDY pin is an open-drain logic output that signals
whether or not the controllers are regulating the output
voltage within the proper levels, and whether any fault
conditions exist. This pin should be tied through a resistor to
a voltage source that’s equal to or less then VCC.
VR_RDY indicates whether VDIFF is within specified
overvoltage and undervoltage limits after a fixed delay from
FIGURE 18. POWER GOOD AND PROTECTION CIRCUITRY
VDIFF
0.50 x DAC
100µA
I
1.280V
AVG
+175mV
DAC
+
-
OCP
+
+
-
-
OVP
AND CONTROL LOGIC
UV
SOFT-START, FAULT
ISL6333 INTERNAL CIRCUITRY
EACH CHANNEL
OCL
REPEAT FOR
OCP
+
-
+
-
140µA
I
VR_RDY
1
V
April 10, 2008
OCP
IMON
FN6520.0