isl6333 Intersil Corporation, isl6333 Datasheet - Page 26

• Manufacturer Part Number: isl6333
• Description: Three-phase Buck Pwm Controller With Integrated Mosfet Drivers And Light Load Efficiency Enhancements For Intel Vr11.1 Applications
• Manufacturer: Intersil Corporation

VID “Off” DAC Codes
The Intel VR11 VID tables include “Off” DAC codes, which
indicate to the controllers to disable all regulation. Recognition
of these codes is slightly different in that they must be stable for
4 consecutive readings of a 5.55MHz clock (540ns to 720ns)
to be recognized. Once an “Off” code is recognized the
controllers latch off, and must be reset by toggling the EN pin.
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on the
FB pin and the COMP pin causes an AC current to flow through
the error amplifier compensation components from the FB to
the COMP pin. This current then flows through the feedback
resistor, R
undershoot at the end of the VID transition. In order to ensure
the smooth transition of the output voltage during a VID
change, a VID-on-the-fly compensation network is required.
This network is composed of a resistor and capacitor in series,
R
This VID-on-the-fly compensation network works by
sourcing AC current into the FB node to offset the effects of
the AC current flowing from the FB to the COMP pin during a
VID transition. To create this compensation current the
controllers set the voltage on the DVC pin to be 2x the
voltage on the REF pin. Since the error amplifier forces the
voltage on the FB pin and the REF pin to be equal, the
resulting voltage across the series RC between DVC and FB
is equal to the REF pin voltage. The RC compensation
components, R
create the desired amount of compensation current.
The amount of compensation current required is dependant
on the modulator gain of the system, K1, and the error
amplifier R-C components, R
between the FB and COMP pins. Use Equations 15, 16, and
17 to calculate the RC component values, R
for the VID-on-the-fly compensation network. For these
equations: V
is the oscillator ramp amplitude (1.5V); and R
DVC
FIGURE 10. DYNAMIC VID COMPENSATION NETWORK
C
REF
REF
and C
VDIFF
FB
DVC
, and can cause the output voltage to overshoot or
DVC
IN
DVC
is the input voltage for the power train; V
V
, between the DVC and the FB pin.
DAC
C
DVC
and C
x2
I
DVC
R
FB
DVC
R
26
C
DVC
, can then be selected to
I
DVC
and C
ISL6333 INTERNAL CIRCUIT
= I
ISL6333, ISL6333A, ISL6333B, ISL6333C
FB
C
C
, that are in series
C
C
+
-
DVC
AMPLIFIER
C
I
ERROR
C
R
and C
C
and C
COMP
C
DVC
are
P-P
,
the error amplifier R-C components between the FB and
COMP pins..
Driver Operation
Adaptive Zero Shoot-Through Deadtime Control
The integrated drivers incorporate an adaptive deadtime control
technique to minimize deadtime and to prevent the upper and
lower MOSFETs from conducting simultaneously. This results
in high efficiency from the reduced freewheeling time of the
lower MOSFET body-diode conduction. This is accomplished
by ensuring either rising gate turns on its MOSFET with
minimum and sufficient delay after the other has turned off.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches 1.75V. At this time the UGATE is
released to rise. Once the PHASE is high, the advanced
adaptive shoot-through circuitry monitors the PHASE and
UGATE voltages during a PWM falling edge and the
subsequent UGATE turn-off. If either the UGATE falls to less
than 1.75V above the PHASE or the PHASE falls to less than
+0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor should have a maximum voltage
rating that’s at least 30% above PVCC and its capacitance
value can be chosen from Equation 18:
where Q
at V
control MOSFETs. The ΔV
allowable droop in the rail of the upper gate drive.
K1
R
C
C
Q
DVC
DVC
BOOT_CAP
GATE
=
GS1
---------- -
V
V
=
=
PP
=
IN
G1
gate-source voltage and N
A R
C
------- -
A
Q
---------------------------------- N
C
×
G1
is the amount of gate charge per upper MOSFET
≥
V
C
------------------------------------- -
ΔV
⋅
GS1
PVCC
BOOT_CAP
A
Q
GATE
=
---------------- -
K1 1
⋅
K1
Q1
–
BOOT_CAP
Q1
term is defined as the
is the number of
April 10, 2008
(EQ. 18)
(EQ. 15)
(EQ. 16)
(EQ. 17)
FN6520.0