isl6333 Intersil Corporation, isl6333 Datasheet - Page 25

• Manufacturer Part Number: isl6333
• Description: Three-phase Buck Pwm Controller With Integrated Mosfet Drivers And Light Load Efficiency Enhancements For Intel Vr11.1 Applications
• Manufacturer: Intersil Corporation

through a load line regulation resistor R
voltage drop across R
effectively creating an output voltage droop with a steady-state
value defined as Equation 9:
The regulated output voltage is reduced by the droop voltage
V
derived by combining Equations 6, 7, 8, and 9.
In Equation 10, V
programmed offset voltage, I
the converter, R
to the ISEN+ pin, R
number of channels, and DCR is the Inductor DCR value.
Therefore the equivalent loadline impedance, i.e. droop
impedance, is equal to Equation 11:
Output-Voltage Offset Programming
The controllers allow the designer to accurately adjust the
offset voltage by connecting a resistor, R
pin to VCC or GND. When R
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I
and out of the FB pin, providing a negative offset. If R
connected to ground, the voltage across it is regulated to
0.3V, and I
providing a positive offset. The offset current flowing through
the resistor between VSEN and FB will generate the desired
offset voltage which is equal to the product (I
These functions are shown in Figures 8 and 9.
V
V
R
V
R
DROOP
DROOP
OUT
LL
OFS
OFS
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
+
-
VDIFF
=
=
------------
R
GND
R
I
. The output voltage as a function of load current is
N
V
OFS
FB
FB
=
OFS
REF
OFS
FB
I
⋅
AVG
-------------- -
R
DCR
PROGRAMMING
–
SET
flows into the FB pin and out of the OFS pin,
ISEN
V
REF
⋅
OFS
R
FB
⋅
ISL6333 INTERNAL CIRCUIT
400
--------- -
FB
FB
is the internal sense resistor connected
3
is the reference voltage, V
–
is the feedback resistor, N is the active
VREF
⎛
⎜
⎝
is proportional to the output current,
I
------------ -
OUT
N
OUT
OFS
25
⋅
OFS
-------------- -
R
DCR
SET
is the total output current of
is connected between OFS
) to flow into the OFS pin
ISL6333, ISL6333A, ISL6333B, ISL6333C
⋅
FB
400
--------- - R
3
. The resulting
OFS
E/A
GND
⋅
+
-
OFS
, from the OFS
FB
0.3V
OFS
⎞
⎟
⎠
x R
VCC
is the
(EQ. 10)
(EQ. 11)
FB
OFS
(EQ. 9)
+
-
1.6V
).
is
Once the desired output offset voltage has been determined,
use Equations 12 and 13 to set R
For Negative Offset (connect R
For Positive Offset (connect R
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the controllers
to do this by making changes to the VID inputs. The
controllers are required to monitor the DAC inputs and
respond to on-the-fly VID changes in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption.
The controllers check for VID changes by comparing the
internal DAC code to the VID pin inputs on the positive edge
of an internal 5.55MHz clock. If a new code is established on
the VID inputs and it remains stable for 3 consecutive
readings (360ns to 540ns), the controllers recognize the new
code and begins incrementing/decrementing the DAC in
6.25mV steps at a stepping frequency of 1.85MHz. This
controlled slew rate of 6.25mV/540ns (11.6mV/µs) continues
until the VID input and DAC are equal. Thus, the total time
required for a VID change, t
of the VID change (ΔV
The time required for a ISL6333-based converter to make a
1.6V to 0.5V reference voltage change is about 95µs, as
calculated using Equation 14.
R
R
t
DVID
V
R
OFS
OFS
OFS
OFS
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
+
-
VDIFF
VCC
=
=
=
I
OFS
R
540 10
--------------------------
V
--------------------------
V
1.6 R
0.3 R
FB
OFS
OFFSET
OFFSET
FB
⋅
⋅
⋅
PROGRAMMING
FB
FB
–
9
⋅
⎛
⎝
ISL6333 INTERNAL CIRCUIT
-------------------- -
0.00625
Δ
VID
V
VREF
VID
).
DVID
⎞
⎠
OFS
, is dependent only on the size
OFS
OFS
to GND):
to VCC):
:
E/A
GND
+
-
0.3V
April 10, 2008
VCC
(EQ. 12)
(EQ. 13)
(EQ. 14)
FN6520.0
+
-
1.6V