isl6333 Intersil Corporation, isl6333 Datasheet - Page 27

• Manufacturer Part Number: isl6333
• Description: Three-phase Buck Pwm Controller With Integrated Mosfet Drivers And Light Load Efficiency Enhancements For Intel Vr11.1 Applications
• Manufacturer: Intersil Corporation

.
Gate Voltage Optimization Technology (GVOT)
(ISL6333, ISL6333B Only)
The ISL6333 and ISL6333B are designed to optimize the
Channel 1 lower MOSFET gate drive voltage to ensure high
efficiency in both normal and low power states. In the normal
power state when the converter load current is high, the
conduction losses of the lower MOSFETs play a large role in
the overall system efficiency. In normal power state, the
lower gate drive voltage should be higher to decrease the
conduction losses of the lower MOSFETs and increase the
system efficiency. In the low power state, where the
converter load current is significantly smaller, MOSFET
driving loss becomes a much higher percentage of power
loss associated with the lower MOSFET. In low power state,
+5V TO
FIGURE 12. INTERNAL GATE DRIVE CONNECTIONS AND
FIGURE 11. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
EXTERNAL CIRCUIT
+12V
+12V
+12V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
1.0µF
20nC
1.0µF
1.0µ
1.0µ
0.1
GAVE VOLTAGE OPTIMIZATION (GVOT)
VOLTAGE
PVCC2_3
F
F
PUVCC
PVCC1
BYP1
0.2
50nC
Q
GATE
0.3
ISL6333, ISL6333B INTERNAL CIRCUIT
= 100nC
ΔV
0.4
27
BOOT_CAP
LVCC = LOWER GATE DRIVE
UVCC = UPPER GATE DRIVE
UVCC1, UVCC2,
LVCC2, LVCC3
0.5
GVOT
REG.
UVCC3
LVCC1
ISL6333, ISL6333A, ISL6333B, ISL6333C
0.6
(V)
0.7
SET BY STATE
OF PSI# AND
0.8
SS PINS
0.9
1.0
the lower gate drive voltage can therefore be reduced to
decrease the driving losses of the lower MOSFETs and
increase the system efficiency.
This gate drive voltage optimization is accomplished by an
internal linear regulator that regulates the Channel 1 lower
gate drive voltage, LVCC1, to certain levels depending on
the state of the PSI# and SS pins. The input and output of
this internal regulator is the PVCC1 pin and BYP1 pin,
respectively. The regulator input, PVCC1, should be
connected to a +12V source and decoupled with a quality
1.0µF ceramic capacitor. The regulator output, BYP1, is
internally connected to the lower gate drive of the Channel 1
MOSFET driver, LVCC1. The BYP1 pin should also be
decoupled using a quality 1.0µF ceramic capacitor..
As Figures 13 and 14 illustrate, the internal regulator has
been designed so that its output voltage, BYP1, is
dependent upon the average load current. In the normal
power state, when PSI# is high, the ISL6333 and ISL6333B
FIGURE 14. BYP1, LVCC1 VOLTAGE WHEN PSI# IS LOW
FIGURE 13. BYP1, LVCC1 VOLTAGE WHEN PSI# IS HIGH
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
0
0
20
20
AVERAGE LOAD CURRENT (mA)
AVERAGE LOAD CURRENT (mA)
40
40
R
60
60
SS
TIED TO GND
R
SS
80
80
+40°C THERMAL
TIED TO VCC
+40°C THERMAL
100
100
April 10, 2008
FN6520.0
120
120