upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 525

• Manufacturer Part Number: upd78f0124m6gba1-8et
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16-bit
timer/
event
counter
00
(TM00)
Function
Valid edge
setting
One-shot pulse
output: Software
trigger
One-shot pulse
output: External
trigger
One-shot pulse
output function
Operation of
OVF00 flag
Conflicting
operations
Timer operation
Capture
operation
Compare
operation
Edge detection
Details of
Function
Set the valid edge of the TI000 pin after clearing bits 2 and 3 (TMC002 and
TMC003) of 16-bit timer mode control register 00 (TMC00) to 0, 0, respectively,
and then stopping timer operation. The valid edge is set using bits 4 and 5
(ES000 and ES001) of prescaler mode register 00 (PRM00).
Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
Do not input the external trigger again while the one-shot pulse is being output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
When using the one-shot pulse output of 16-bit timer/event counter 00 with a
software trigger, do not change the level of the TI000 pin or its alternate-function
port pin.
Because the external trigger is valid even in this case, the timer is cleared and
started even at the level of the TI000 pin or its alternate-function port pin, resulting
in the output of a pulse at an undesired timing.
The OVF00 flag is also set to 1 in the following case.
When any of the following modes is selected: the mode in which clear & start
occurs on a match between TM00 and CR000, the mode in which clear & start
occurs at the TI000 valid edge, or the free-running mode
→ CR000 is set to FFFFH
→ TM00 is counted up from FFFFH to 0000H.
Even if the OVF00 flag is cleared before the next count clock is counted (before
TM00 becomes 0001H) after the occurrence of TM00 overflow, the OVF00 flag is
re-set newly so this clear is invalid.
If a conflict occurs between the read period of the 16-bit timer capture/compare
register (CR000/CR010) and capture trigger input (CR000/CR010 used as capture
register), the priority is given to the capture trigger input. The data read from
CR000/CR010 is undefined.
Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit
timer capture/compare register 010 (CR010).
Regardless of the CPU’s operation mode, when the timer stops, the input signals
to the TI000/TI010 pins are not acknowledged.
The one-shot pulse output mode operates correctly only in the free-running mode
and the mode in which clear & start occurs at the TI000 valid edge. In the mode in
which clear & start occurs on a match between the TM00 register and CR000
register, one-shot pulse output is not possible because an overflow does not
occur.
If TI000 valid edge is specified as the count clock, a capture operation by the
capture register specified as the trigger for TI000 is not possible.
To ensure the reliability of the capture operation, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode
register 00 (PRM00).
The capture operation is performed at the falling edge of the count clock. An
interrupt request input (INTTM000/INTTM010), however, is generated at the rise
of the next count clock.
A capture operation may not be performed for CR000/CR010 set in compare
mode even if a capture trigger has been input.
If the TI000 or TI010 pin is high level immediately after system reset and the rising
edge or both the rising and falling edges are specified as the valid edge of the
TI000 or TI010 pin to enable the 16-bit timer counter 00 (TM00) operation, a rising
edge is detected immediately after the operation is enabled. Be careful therefore
when pulling up the TI000 or TI010 pin. However, if the TI000 pin or TI010 pin is
high level when re-enabling operation after the operation has been stopped, the
rising edge is not detected.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16315EJ3V1UD
Cautions
p. 165
p. 165
p. 165
p. 165
p. 166
p. 166
p. 166
p. 167
p. 167
p. 167
p. 167
p. 167
p. 167
p. 167
p. 167
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