upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 106

• Manufacturer Part Number: upd78f0124m6gba1-8et
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

106
Notes 1.
Caution Be sure to clear bit 3 to 0.
Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
Address: FFFBH
Symbol
PCC
2.
3.
4.
5.
2. f
3. f
4. f
5. f
Bit 5 is read-only.
When the CPU is operating on the subsystem clock, MCC should be used to stop the X1 oscillator
operation. When the CPU is operating on the internal oscillation clock, use bit 7 (MSTOP) of the main
OSC control register (MOC) to stop the X1 oscillator operation (this cannot be set by MCC). A STOP
instruction should not be used.
Clear this bit to 0 when the subsystem clock is used and set to 1 when the subsystem clock is not
used.
Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register
(MCM) are 1.
Setting is prohibited for the (A1) and (A2) grade products.
X
R
XP
XT
: Main system clock oscillation frequency (X1 input clock oscillation frequency or internal
: Internal oscillation clock frequency
: X1 input clock oscillation frequency
: Subsystem clock oscillation frequency
CSS
MCC
MCC
FRC
CLS
<7>
oscillation clock frequency)
0
1
0
1
0
1
0
1
Note 4
After reset: 00H
Figure 5-2. Format of Processor Clock Control Register (PCC)
Oscillation possible
Oscillation stopped
On-chip feedback resistor used
On-chip feedback resistor not used
X1 input clock or internal oscillation clock
Subsystem clock
PCC2
FRC
<6>
Other than above
0
0
0
0
1
0
0
0
0
1
R/W
CHAPTER 5 CLOCK GENERATOR
PCC1
CLS
<5>
Note 1
User’s Manual U16315EJ3V1UD
0
0
1
1
0
0
0
1
1
0
Subsystem clock feedback resistor selection
Control of X1 oscillator operation
PCC0
CSS
<4>
0
1
0
1
0
0
1
0
1
0
Note 3
CPU clock status
f
f
f
f
f
f
Setting prohibited
X
X
X
X
X
XT
/2
/2
/2
/2
/2
2
3
4
3
0
CPU Clock (f
PCC2
f
f
Setting prohibited
Setting prohibited
Setting prohibited
2
R
R
/2
Note 2
MCM0 = 0
Note 5
CPU
) Selection
PCC1
1
f
f
f
f
f
XP
XP
XP
XP
XP
/2
/2
/2
/2
MCM0 = 1
2
3
4
PCC0
0