upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 521

• Manufacturer Part Number: upd78f0124m6gba1-8et
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Internal
oscillator
Main clock
Subsystem
clock
Main clock
Subsystem
clock
Main clock
Function
−
PCC:
Processor clock
control register
(PCC)
RCM: Internal
oscillation
mode register
MCM: Main
clock mode
register
MOC: Main
OSC control
register
OSTC:
Oscillation
stabilization
time counter
status register
OSTS:
Oscillation
stabilization
time select
register
Details of
Function
Be sure to clear bit 3 to 0.
Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before
setting RSTOP.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the divided clock of the internal oscillator output (f
peripheral hardware (f
Operation of the peripheral hardware with the internal oscillation clock cannot be
guaranteed. Therefore, when the internal oscillation clock is selected as the clock
supplied to the CPU, do not use peripheral hardware. In addition, stop the
peripheral hardware before switching the clock supplied to the CPU from the X1
input clock to the internal oscillation clock. Note, however, that the following
peripheral hardware can be used when the CPU operates on the internal
oscillation clock.
• Watchdog timer
• Clock monitor
• 8-bit timer H1 when f
• Peripheral hardware selecting external clock as the clock source
(Except when external count clock of TM00 is selected (TI000 valid edge))
Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to X1
input clock operation (bit 4 (CSS) of the processor clock control register (PCC) is
changed from 1 to 0).
Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before
setting MSTOP.
To stop X1 oscillation when the CPU is operating on the subsystem clock, set bit 7
(MCC) of the processor clock control register (PCC) to 1 (setting by MSTOP is not
possible).
After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
If the STOP mode is entered and then released while the internal oscillation clock
is being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
To set the STOP mode while the X1 input clock is used as the CPU clock, set
OSTS before executing the STOP instruction.
Before setting OSTS, confirm with OSTC that the desired oscillation stabilization
time has elapsed.
If the STOP mode is entered and then released while the internal oscillation clock
is being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
OSTS
by OSTS
APPENDIX D LIST OF CAUTIONS
User’s Manual U16315EJ3V1UD
X
R
/2
= 240 kHz (TYP.)).
7
is selected as count clock
Cautions
X
) is supplied to the
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