74VCX16821MTDX Fairchild Semiconductor, 74VCX16821MTDX Datasheet

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74VCX16821MTDX

Manufacturer Part Number
74VCX16821MTDX
Description
IC FLIP FLOP 20BIT D LV 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74VCXr
Type
D-Type Busr
Datasheet
1.74VCX16821MTDX.pdf (9 pages)

Specifications of 74VCX16821MTDX

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
2
Number Of Bits Per Element
10
Frequency - Clock
250MHz
Delay Time - Propagation
1.5ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2004 Fairchild Semiconductor Corporation
74VCX16821MTD
74VCX16821
Low Voltage 20-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16821 contains twenty non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications.
The 74VCX16821 is designed for low voltage (1.4V to
3.6V) V
The 74VCX16821 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with I/O compatibility up to 3.6V.
Package Number
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500130
Features
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
value of the resistor is determined by the current-sourcing capability of the
driver.
Pin Descriptions
OE
CLK
D
O
1.4V to 3.6V V
3.6V tolerant inputs and outputs
t
Power-off high impedance inputs and outputs
Supports live insertion and withdrawal (Note 1)
Static Drive (I
Uses patented noise/EMI reduction circuitry
Latch-up performance exceeds 300 mA
ESD performance:
0
0
PD
Pin Names
–D
–O
n
3.5 ns max for 3.0V to 3.6V V
Human body model
Machine model
n
24 mA @ 3.0V V
19
Package Descriptions
19
OH
CC
Output Enable Input (Active LOW)
Clock Input
Inputs
Outputs
/I
OL
supply operation
)
200V
CC
CC
2000V
through a pull-up resistor; the minimum
March 1998
Revised October 2004
Description
CC
www.fairchildsemi.com

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74VCX16821MTDX Summary of contents

Page 1

... MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2004 Fairchild Semiconductor Corporation Features 1.4V to 3.6V V supply operation CC 3.6V tolerant inputs and outputs ...

Page 2

Connection Diagram Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com Truth Tables Inputs CLK OE D – ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 3) 0. Input Diode Current ( Output ...

Page 4

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power-OFF Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC Note ...

Page 5

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency C MAX Propagation Delay C PHL L t PLH Output Enable Time C PZL L t PZH Output Disable Time C ...

Page 6

Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP OL V Quiet Output Dynamic Valley V OLV OL V Quiet Output Dynamic Valley V OHV OH Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low ...

Page 8

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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